HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 288

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

10.4.8
In the buffer mode, the buffer operation functions differ depending on whether the general
registers are set to output compare or input capture, the reset-synchronized PWM mode, or
complementary PWM mode. The buffer mode is a function of channels 3 and 4 only. Buffer
operations set this way function as follows.
GR is an Output Compare Register: The value of the buffer registers of a channel is transferred
to the GR when the channel experiences a compare match. This is illustrated in figure 10.45.
GR is an Input Capture Register: TCNT values are transferred to GR when input capture occurs
and the value previously stored in GR is transferred to BR. This operation is illustrated in figure
10.46.
274 HITACHI
Figure 10.44 Phase Differentials, Overlap and Pulse Width in the Phase Counting Mode
TCLKA
TCLKB
BR
Buffer Mode
differential
Phase
Figure 10.45 Compare Match Buffer Operation
Overlap
Compare match signal
differential
Phase
GR
Overlap
Phase differential, overlap: 1.5 cycles minimum
Pulse width: 2.5 cycles minimum
Pulse
width
Comparator
Pulse
width
TCNT