HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 361

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

13.2.6
The serial control register (SCR) enables the SCI transmitter/receiver, selects serial clock output in
the asynchronous mode, enables and disables interrupts, and selects the transmit/receive clock
source. The CPU can always read and write the SCR. The SCR is initialized to H'00 by a reset or
in standby mode.
•
Bit 7: TIE
0
1
•
Bit 6: RIE
0
1
HITACHI 348
Bit 7 (transmit interrupt enable (TIE)): TIE enables or disables the transmit-data-empty
interrupt (TXI) requested when the transmit data register empty bit (TDRE) in the serial status
register (SSR) is set to 1 due to transfer of serial transmit data from the TDR to the TSR.
Bit 6 (receive interrupt enable (RIE)): RIE enables or disables the receive-data-full interrupt
(RXI) requested when the receive data register full bit (RDRF) in the serial status register
(SSR) is set to 1 due to transfer of serial receive data from the RSR to the RDR. Also enables
or disables receive-error interrupt (ERI) requests.
Initial value:
Bit name:
Serial Control Register
R/W:
Bit:
R/W
TIE
7
0
Description
Transmit-data-empty interrupt request (TXI) is disable. The TXI
interrupt request can be cleared by reading TDRE after it has been set
to 1, then clearing TDRE to 0, or by clearing TIE to 0 (initial value).
Transmit-data-empty interrupt request (TXI) is enabled
Description
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI)
requests are disabled. RXI and ERI interrupt requests can be cleared
by reading the RDRF flag or error flag (FER, PER, or ORER) after it
has been set to 1, then clearing the flag to 0, or by clearing RIE to 0
(initial value).
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI)
requests are enabled
R/W
RIE
6
0
R/W
TE
5
0
R/W
RE
4
0
MPIE
R/W
3
0
TEIE
R/W
2
0
CKE1
R/W
1
0
CKE0
R/W
0
0