HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 364

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

13.2.7
The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status
flags that indicate SCI operating status.
The CPU can always read and write the SSR, but cannot write 1 in the status flags (TDRE, RDRF,
ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after
being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. The SSR is
initialized to H'84 by a reset or in standby mode.
Note: Write 0 to clear flag.
•
Bit 7: TDRE
0
1
Bit 7 (transmit data register empty (TDRE)): TDRE indicates that the SCI has loaded transmit
data from the TDR into the TSR and serial transmit new data can be written in the TDR.
Initial value:
Bit name:
Serial Status Register
R/W:
Bit:
Description
TDR contains valid transmit data
TDRE is cleared to 0 when:
• Software reads TDRE after it has been set to 1, then writes 0 in TDRE
• The DMAC writes data in TDR
TDR does not contain valid transmit data (initial value)
TDRE is set to 1 when:
• The chip is reset or enters standby mode
• The TE bit in the serial control register (SCR) is cleared to 0
• TDR contents are loaded into TSR, so new data can be written in TDR
R/(W)*
TDRE
7
1
R/(W)*
RDRF
6
0
R/(W)*
ORER
5
0
R/(W)*
FER
4
0
R/(W)*
PER
3
0
TEND
2
1
R
MPB
1
0
R
HITACHI 351
MPBT
R/W
0
0