HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 368

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

13.2.8
The bit rate register (BRR) is an eight-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write the BRR. The BRR is initialized to H'FF by a reset or in
standby mode. SCI1 and SCI2 have independent baud rate generator control, so different values
can be set in the two channels.
Table 13.3 shows examples of BRR settings in the asynchronous mode; table 13.4 shows
examples of BBR settings in the clocked synchronous mode.
Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode
Bit Rate
(bits/s)
110
150
300
600
1200
2400
4800
9600
19200
31250
38400
Initial value:
Bit name:
Bit Rate Register (BRR)
R/W:
n
1
1
0
0
0
0
0
—
—
0
—
Bit:
R/W
7
1
N
141
103
207
103
51
25
12
—
—
1
—
R/W
6
1
2
Error (%)
0.03
0.16
0.16
0.16
0.16
0.16
0.16
—
—
0.00
—
R/W
5
1
R/W
4
1
(MHz)
n
1
1
0
0
0
0
0
0
—
—
—
R/W
3
1
N
148
108
217
108
54
26
13
6
—
—
—
R/W
2
1
2.097152
R/W
Error (%)
–0.04
0.21
0.21
0.21
–0.70
1.14
–2.48
–2.48
—
—
—
1
1
HITACHI 355
R/W
0
1