HD643303x Hitachi, HD643303x Datasheet - Page 207

• Manufacturer Part Number: HD643303x
• Description: Hitachi Microcomputer
• Manufacturer: Hitachi

8.2.6 Timer Output Control Register (TOCR)
TOCR is an 8-bit readable/writable register that selects externally triggered disabling of output in
complementary PWM mode and reset-synchronized PWM mode, and inverts the output levels.
The settings of the XTGD, OLS4, and OLS3 bits are valid only in complementary PWM mode
and reset-synchronized PWM mode. These settings do not affect other modes.
TOCR is initialized to H'FF by a reset and in standby mode.
Bits 7 to 5—Reserved: Read-only bits, always read as 1.
Bit 4—External Trigger Disable (XTGD): Selects externally triggered disabling of ITU output
in complementary PWM mode and reset-synchronized PWM mode.
Bit 4
XTGD
0
1
Bit
Initial value
Read/Write
Description
Input capture A in channel 1 is used as an external trigger signal in complementary PWM
mode and reset-synchronized PWM mode.
When an external trigger occurs, bits 5 to 0 in the timer output master enable register
(TOER) are cleared to 0, disabling ITU output.
External triggering is disabled
—
—
7
1
Reserved bits
—
—
6
1
External trigger disable
Selects externally triggered disabling of output in
complementary PWM mode and reset-synchronized
PWM mode
—
—
5
1
192
XTGD
R/W
4
1
Reserved bits
—
—
3
1
—
—
Output level select 3, 4
These bits select output
levels in complementary
PWM mode and reset-
synchronized PWM mode
2
1
OLS4
R/W
1
1
(Initial value)
OLS3
R/W
0
1