HD643303x Hitachi, HD643303x Datasheet - Page 295

• Manufacturer Part Number: HD643303x
• Description: Hitachi Microcomputer
• Manufacturer: Hitachi

9.2.8 Next Data Enable Register B (NDERB)
NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2
(TP
If a bit is enabled for TPC output by NDERB, then when the ITU compare match event selected in
the TPC output control register (TPCR) occurs, the NDRB value is automatically transferred to
the corresponding PBDR bit, updating the output value. If TPC output is disabled, the bit value is
not transferred from NDRB to PBDR and the output value does not change.
NDERB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable TPC
output groups 3 and 2 (TP
Bits 7 to 0
NDER15 to NDER8
0
1
Bit
Initial value
Read/Write
15
to TP
8
) on a bit-by-bit basis.
NDER15
R/W
7
0
Description
TPC outputs TP
(NDR15 to NDR8 are not transferred to PB
TPC outputs TP
(NDR15 to NDR8 are transferred to PB
15
NDER14
to TP
R/W
6
0
8
) on a bit-by-bit basis.
NDER13
R/W
15
15
5
0
to TP
to TP
Next data enable 15 to 8
These bits enable or disable
TPC output groups 3 and 2
NDER12
280
8
8
R/W
are disabled
are enabled
4
0
NDER11
R/W
3
0
7
to PB
NDER10
7
to PB
R/W
2
0
0
)
0
)
NDER9
R/W
1
0
(Initial value)
NDER8
R/W
0
0