HD643303x Hitachi, HD643303x Datasheet - Page 306

• Manufacturer Part Number: HD643303x
• Description: Hitachi Microcomputer
• Manufacturer: Hitachi

Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non-
Overlapping Output): Figure 9-7 shows an example of the use of TPC output for four-phase
complementary non-overlapping pulse output.
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•
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Figure 9-7 Non-Overlapping TPC Output Example (Four-Phase Complementary
GRB
GRA
H'0000
NDRB
PBDR
TP
TP
TP
TP
TP
TP
TP
TP
The ITU channel to be used as the output trigger channel is set up so that GRA and GRB are output
compare registers and the counter will be cleared by compare match B. The TPC output trigger
period is set in GRB. The non-overlap margin is set in GRA. The IMIEA bit is set to 1 in TIER to enable
IMFA interrupts.
H'FF is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set
Bits G3NOV and G2NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is
written in NDRB.
The timer counter in this ITU channel is started. When compare match B occurs, outputs change from
1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed
by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRB.
Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95…
at successive IMFA interrupts.
15
14
13
12
11
10
9
8
TCNT value
TCNT
95
00
95
65
05
Non-Overlapping Pulse Output)
Non-overlap margin
65
59
41
59
291
56
50
56
95
14
95
65
05
65
Time