HD643303x Hitachi, HD643303x Datasheet - Page 543

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HD643303x

Manufacturer Part Number
HD643303x
Description
Hitachi Microcomputer
Manufacturer
Hitachi
Datasheet
SYSCR—System Control Register
Bit
Initial value
Read/Write
SSBY
Software standby
R/W
0 SLEEP instruction causes transition to sleep mode
1 SLEEP instruction causes transition to software standby mode
7
0
Standby timer select 2 to 0
STS2
Bit 6
STS2
R/W
0
1
6
0
STS1
Bit 5
0
1
0
1
STS1
User bit enable
R/W
0 CCR bit 6 (UI) is used as an interrupt mask bit
1 CCR bit 6 (UI) is used as a user bit
5
0
NMI edge select
STS0
0 An interrupt is requested at the falling edge of NMI
1 An interrupt is requested at the rising edge of NMI
Bit 4
0
1
0
1
528
STS0
R/W
Standby Timer
Waiting time = 8192 states
Waiting time = 16384 states
Waiting time = 32768 states
Waiting time = 65536 states
Waiting time = 131072 states
Illegal setting
4
0
R/W
UE
3
1
H'F2
RAM enable
NMIEG
0 On-chip RAM is disabled
1 On-chip RAM is enabled
R/W
2
0
System control
1
1
RAME
R/W
0
1

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