HD643303x Hitachi, HD643303x Datasheet - Page 570

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HD643303x

Manufacturer Part Number
HD643303x
Description
Hitachi Microcomputer
Manufacturer
Hitachi
Datasheet
Reset in T
T
the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state. The
address bus outputs are held during the T
the T
3
RD (read access)
(mode 1)
WR (write access)
(mode 1)
Data bus
(write access)
(mode 1)
I/O port
(modes 1 to 3)
Internal
reset signal
Address bus
(mode 1)
AS (mode 1)
ø
RES
state of an external memory access cycle. As soon as RES goes low, all ports are initialized to
2
state of an access cycle to a two-state-access area.
3
State: Figure D-3 is a timing diagram for the case in which RES goes low during the
Figure D-3 Reset during Memory Access (Reset during T
3
Access to external address
state.The same timing applies when a reset occurs in
T
1
554
T
2
T
3
3
State)
High impedance
High impedance
H'000000

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