HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 117

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

Figure 5-5 shows the transitions among the above states.
Figure 5-6 is a flowchart showing how interrupts are accepted when UE = 0.
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If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
When the interrupt controller receives one or more interrupt requests, it selects the highest-
priority request, following the IPR interrupt priority settings, and holds other requests
pending. If two or more interrupts with the same IPR setting are requested simultaneously, the
interrupt controller follows the priority order shown in table 5-3.
The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt
request is accepted regardless of its IPR setting, and regardless of the UI bit. If the I bit is set
to 1 and the UI bit is cleared to 0, only NMI and interrupts with priority level 1 are accepted;
interrupt requests with priority level 0 are held pending. If the I bit and UI bit are both set to
1, only NMI is accepted; all other interrupt requests are held pending.
When an interrupt request is accepted, interrupt exception handling starts after execution of
the current instruction has been completed.
In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is
saved indicates the address of the first instruction that will be executed after the return from
the interrupt service routine.
The I and UI bits are set to 1 in CCR, masking all interrupts except NMI.
The vector address of the accepted interrupt is generated, and the interrupt service routine
starts executing from the address indicated by the contents of the vector address.
a.
All interrupts are
unmasked
Figure 5-5 Interrupt Masking State Transitions (Example)
I
0
Exception handling,
or I
1, UI
c.
All interrupts are
masked except NMI
I
1
I
103
1, UI
0
0
UI
0
b.
Only NMI, IRQ , and
IRQ are unmasked
Exception handling,
or UI
3
1
2