HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 157

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

Figure 6-19 shows the timing when the bus right is requested by an external bus master during a
read cycle in a two-state-access area. There is a minimum interval of two states from when the
BREQ signal goes low until the bus is released.
Figure 6-19 External-Bus-Released State (Two-State-Access Area, During Read Cycle)
ø
Address
bus
CS
Data bus
AS
HWR
BREQ
BACK
n = 7 to 0
1
2
3
4, 5
6
n
,
RD
Low
BACK
BREQ
High
BREQ
,
LWR
BREQ
BREQ
signal goes low at end of CPU read cycle, releasing bus right to external bus master.
pin continues to be sampled while bus is released to external bus master.
signal goes high, ending bus-release cycle.
High
signal is sampled twice consecutively.
signal is sampled at rise of T state.
1
CPU cycles
Minimum 2 cycles
T
1
Address
T
2
1
2
143
3
External bus released
High-impedance
High-impedance
High-impedance
High-impedance
High level
4
5
6
CPU cycles