HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 178

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

Operation in Power-Down State: The refresh controller operates in sleep mode. It does not
operate in hardware standby mode. In software standby mode RTCNT is initialized, but RFSHCR,
RTMCSR bits 5 to 3, and RTCOR retain their settings prior to the transition to software standby
mode.
Example 1: Connection to 2WE 1-Mbit DRAM (1-Mbyte Mode): Figure 7-7 shows typical
interconnections to a 2WE 1-Mbit DRAM, and the corresponding address map. Figure 7-8 shows
a setup procedure to be followed by a program for this example. After power-up the DRAM must
be refreshed to initialize its internal state. Initialization takes a certain length of time, which can
be measured by using an interrupt from another timer module, or by counting the number of times
RTMCSR bit 7 (CMF) is set. Note that no refresh cycle is executed for the first refresh request
after exit from the reset state or standby mode (the first time the CMF flag is set; see figure 7-3).
When using this example, check the DRAM device characteristics carefully and use a procedure
that fits them.
Figure 7-7 Interconnections and Address Map for 2WE 1-Mbit DRAM (Example)
H8/3048 Series
H'60000
H'7FFFF
D
15
to D
HWR
LWR
CS
RD
A
A
A
A
A
A
A
A
8
7
6
5
4
3
2
1
3
0
DRAM area
a. Interconnections (example)
b. Address map
164
Area 3 (1-Mbyte mode)
A
A
A
A
A
A
A
A
RAS
CAS
UW
LW
OE
I/O
7
6
5
4
3
2
1
0
15
2
to I/O
WE
16-bit organization
1-Mbit DRAM with
0