HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 187

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

Refresh Cycle Priority Order: When there are simultaneous bus requests, the priority order is:
For details see section 6.3.7, Bus Arbiter Operation.
Wait State Insertion: When bit AST3 is set to 1 in ASTCR, the wait state controller (WSC) can
insert wait states into bus cycles and refresh cycles. For details see section 6.3.5, Wait Modes.
Self-Refresh Mode: Some pseudo-static RAM devices have a self-refresh function. After the
SRFMD bit is set to 1 in RFSHCR, when a transition to software standby mode occurs, the
H8/3048 Series’ CS
RAM self-refresh function can be used. On exit from software standby mode, the RFSH output
goes high.
Table 7-8 shows the pin states in software standby mode. Figure 7-16 shows the signal output
timing.
Table 7-8 Pin States in Software Standby Mode (2) (PSRAME = 1, DRAME = 0)
Signal
CS
RD
HWR
LWR
RFSH
3
(High)
External bus master > refresh controller > DMA controller > CPU
3
output goes high and its RFSH output goes low so that the pseudo-static
SRFMD = 0
High
High-impedance
High-impedance
High-impedance
High
Software Standby Mode
173
SRFMD = 1 (Self-Refresh Mode)
High
High-impedance
High-impedance
High-impedance
Low
(Low)