HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 197

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HD6433044

Manufacturer Part Number
HD6433044
Description
(HD64 Series) Hitachi Single-Chip Microcomputer
Manufacturer
Hitachi Semiconductor
Datasheet

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7.4 Interrupt Source
Compare match interrupts (CMI) can be generated when the refresh controller is used as an
interval timer. Compare match interrupt requests are masked/unmasked with the CMIE bit of
RTMCSR.
7.5 Usage Notes
When using the DRAM or pseudo-static RAM refresh function, note the following points:
Note: * When the DRAM enable bit (DRAME) or PSRAM enable bit (PSRAME) in the refresh
Address bus
P8
P8
0
1
/RFSH/IRQ
/CS
With the refresh controller, if directly connected DRAM or PSRAM is disconnected*, the
P8
simultaneously.
Refresh cycles are not executed while the bus is released, during software standby mode, and
when a bus cycle is greatly prolonged by insertion of wait states. When these conditions
occur, other means of refreshing are required.
If refresh requests occur while the bus is released, the first request is held and one refresh
cycle is executed after the bus-released state ends. Figure 7-24 shows the bus cycles in this
case.
0
/RFSH/IRQ
3
control register (RFSHCR) is cleared to 0 after being set to 1.
/IRQ
Figure 7-23 Operation when DRAM/PSRAM Connection is Switched
1
0
0
pin and the P8
1
/CS
3
/IRQ
1
183
pin may both become low-level outputs
Area 3 start address

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