HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 229

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

8.4.5 Normal Mode
In normal mode the A and B channels are combined. One byte or word is transferred per request.
A designated number of these transfers are executed. Addresses are specified in MARA and
MARB. Table 8-9 indicates the register functions in I/O mode.
Table 8-9 Register Functions in Normal Mode
Register
Legend
MARA:
MARB:
ETCRA: Execute transfer count register A
The source and destination addresses are both 24-bit addresses. MARA specifies the source
address. MARB specifies the destination address. MARA and MARB can be independently
incremented, decremented, or held fixed as data is transferred.
The transfer count is specified as a 16-bit value in ETCRA. The ETCRA value is decremented by
1 at each transfer. When the ETCRA value reaches H'0000, the DTE bit is cleared and the transfer
ends. If the DTIE bit is set, a CPU interrupt is requested at this time. The maximum transfer count
is 65,536, obtained by setting ETCRA to H'0000.
Figure 8-8 illustrates how normal mode operates.
23
23
Memory address register A
Memory address register B
15
MARA
MARB
ETCRA
0
0
0
Function
Source address
register
Destination
address register
Transfer counter
215
Initial Setting
Source address
Destination
address
Number of
transfers
Operation
Incremented or
decremented once per
transfer, or held fixed
Incremented or
decremented once per
transfer, or held fixed
Decremented once per
transfer