HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 232

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

8.4.6 Block Transfer Mode
In block transfer mode the A and B channels are combined. One block of a specified size is
transferred per request. A designated number of block transfers are executed. Addresses are
specified in MARA and MARB. The block area address can be either held fixed or cycled.
Table 8-10 indicates the register functions in block transfer mode.
Table 8-10 Register Functions in Block Transfer Mode
Register
Legend
MARA:
MARB:
ETCRA: Execute transfer count register A
ETCRB: Execute transfer count register B
The source and destination addresses are both 24-bit addresses. MARA specifies the source
address. MARB specifies the destination address. MARA and MARB can be independently
incremented, decremented, or held fixed as data is transferred. One of these registers operates as a
block area register: even if it is incremented or decremented, it is restored to its initial value at the
end of each block transfer. The TMS bit in DTCRB selects whether the block area is the source or
destination.
23
23
Memory address register A
Memory address register B
15
MARA
MARB
ETCRB
7
ETCRAH
7
ETCRAL
0
0
0
0
0
Function
Source address
register
Destination
address register
Block size counter Block size
Initial block size
Block transfer
counter
218
Initial Setting
Source address
Destination
address
Block size
Number of block
transfers
Operation
Incremented or
decremented once per
transfer, or held fixed
Incremented or
decremented once per
transfer, or held fixed
Decremented once per
transfer until H'00 is
reached, then reloaded
from ETCRAL
Held fixed
Decremented once per
block transfer until H'0000
is reached and the
transfer ends