HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 252

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HD6433044

Manufacturer Part Number
HD6433044
Description
(HD64 Series) Hitachi Single-Chip Microcomputer
Manufacturer
Hitachi Semiconductor
Datasheet

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8.6 Usage Notes
8.6.1 Note on Word Data Transfer
Word data cannot be accessed starting at an odd address. When word-size transfer is selected, set
even values in the memory and I/O address registers (MAR and IOAR).
8.6.2 DMAC Self-Access
The DMAC itself cannot be accessed during a DMAC cycle. DMAC registers cannot be specified
as source or destination addresses.
8.6.3 Longword Access to Memory Address Registers
A memory address register can be accessed as longword data at the MARR address.
Example
MOV.L
MOV.L
Four byte accesses are performed. Note that the CPU may release the bus between the second byte
(MARE) and third byte (MARH).
Memory address registers should be written and read only when the DMAC is halted.
8.6.4 Note on Full Address Mode Setup
Full address mode is controlled by two registers: DTCRA and DTCRB. Care must be taken to
prevent the B channel from operating in short address mode during the register setup. The enable
bits (DTE and DTME) should not be set to 1 until the end of the setup procedure.
#LBL, ER0
ER0, @MARR
238

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