HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 399

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HD6433044

Manufacturer Part Number
HD6433044
Description
(HD64 Series) Hitachi Single-Chip Microcomputer
Manufacturer
Hitachi Semiconductor
Datasheet

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ø
Address bus
Internal write signal
Input capture signal
TCNT
GR
Contention between General Register Write and Input Capture: If an input capture signal
occurs in the T
the general register is not performed. See figure 10-68.
Note on Waveform Period Setting: When a counter is cleared by compare match, the counter is
cleared in the last state at which the TCNT value matches the general register value, at the time
when this value would normally be updated to the next count. The actual counter frequency is
therefore given by the following formula:
f =
(f: counter frequency. ø: system clock frequency. N: value set in general register.)
Figure 10-68 Contention between General Register Write and Input Capture
(N + 1)
ø
3
state of a general register write cycle, input capture takes priority and the write to
General register write cycle
T
1
GR address
T
2
M
387
T
3
M

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