HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 427

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 11-5 shows
an example in which the TPC is used for cyclic five-phase pulse output.
GRA
H'0000
NDRB
PBDR
TP
TP
TP
TP
TP
•
•
•
•
TCNT value
15
14
13
12
11
The ITU channel to be used as the output trigger channel is set up so that GRA is an output compare
register and the counter will be cleared by compare match A. The trigger period is set in GRA.
The IMIEA bit is set to 1 in TIER to enable the compare match A interrupt.
H'F8 is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in
TPCR to select compare match in the ITU channel set up in step 1 as the output trigger.
Output data H'80 is written in NDRB.
The timer counter in this ITU channel is started. When compare match A occurs, the NDRB contents
are transferred to PBDR and output. The compare match/input capture A (IMFA) interrupt service routine
Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing
H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88… at successive IMFA interrupts. If the DMAC is set for
activation by this interrupt, pulse output can be obtained without loading the CPU.
writes the next output data (H'C0) in NDRB.
00
80
Figure 11-5 Normal TPC Output Example (Five-Phase Pulse Output)
80
TCNT
C0
C0
40
40
60
Compare match
60
20
20
30
415
30
10
10
18
18
08
08
88
88
80
80
C0
C0
40
Time