HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 460

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

Bit 4—Receive Enable (RE): Enables or disables the start of SCI serial receiving operations.
Bit 4
RE
0
1
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE setting is valid only in asynchronous mode, and only if the MP bit is set to 1 in SMR.
The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to 0.
Bit 3
MPIE
0
1
Note: * The SCI does not transfer receive data from RSR to RDR, does not detect receive errors,
2. In the enabled state, serial receiving starts when a start bit is detected in asynchronous
and does not set the RDRF, FER, and ORER flags in SSR. When it receives data in which
MPB = 1, the SCI sets the MPB bit to 1 in SSR, automatically clears the MPIE bit to 0,
enables RXI and ERI interrupts (if the RIE bit is set to 1 in SCR), and allows the FER and
ORER flags to be set.
Description
Receiving disabled
Receiving enabled
Description
Multiprocessor interrupts are disabled (normal receive operation)
[Clearing conditions]
The MPIE bit is cleared to 0.
MPB = 1 in received data.
Multiprocessor interrupts are enabled*
Receive-data-full interrupts (RXI), receive-error interrupts (ERI), and setting of the RDRF,
FER, and ORER status flags in SSR are disabled until data with the multiprocessor bit
set to 1 is received.
flags retain their previous values.
mode, or serial clock input is detected in synchronous mode. Select the receive format
in SMR before setting the RE bit to 1.
*2
*1
449
(Initial value)
(Initial value)