HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 517

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HD6433044

Manufacturer Part Number
HD6433044
Description
(HD64 Series) Hitachi Single-Chip Microcomputer
Manufacturer
Hitachi Semiconductor
Datasheet

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The operating sequence is as follows.
1. When not in use, the data line is in the high-impedance state, and is pulled up to the high level
2. To start transmitting a frame of data, the transmitting device transmits a low start bit (Ds),
3. Next, in the smart card interface, the transmitting device returns the data line to the high-
4. The receiving device performs a parity check. If there is no parity error, the receiving device
5. If the transmitting device does not receive an error signal, it proceeds to transmit the next
through a resistor.
followed by eight data bits (D0 to D7) and a parity bit (Dp).
impedance state. The data line is pulled up to the high level through a resistor.
waits to receive the next data. If a parity error is present, the receiving device outputs a low
error signal (DE) to request retransmission of the data. After outputting the error signal for a
designated interval, the receiving device returns the signal line to the high-impedance state.
The signal line is pulled back up to the high level through the pull-up resistor.
data. If it receives an error signal, it returns to step 2 and transmits the same data again.
507

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