HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 523

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

TEND flag is set to 1, a transmit-data-empty interrupt (TXI) is requested. If the RIE bit is set to 1
to enable interrupt requests, when a transmit error occurs and the ERS flag is set to 1, a
transmit/receive-error interrupt (ERI) is requested.
The timing of TEND flag setting depends on the GM bit in SMR. The timing is shown in figure
14-6.
If the TXI interrupt activates the DMAC, the number of bytes designated in the DMAC can be
transmitted automatically, including automatic retransmit.
For details, see Interrupt Operations and Data Transfer by DMAC in this section.
No
No
No
Figure 14-4 Transmit Flowchart (Example)
Write data in TDR and clear
TDRE flag to 0 in SSR
Start transmitting
Clear TE bit to 0
FER/ERS = 0 ?
FER/ERS = 0 ?
transmitted ?
TEND = 1 ?
TEND = 1 ?
Initialize
All data
Start
End
Yes
Yes
Yes
Yes
Yes
513
No
No
Error handling
Error handling