HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 532

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

Retransmission when SCI is in Transmit Mode (See Figure 14-12):
(6) After transmitting one frame, if the receiving device returns an error signal, the SCI sets the
(7) The TEND bit in SSR is not set for the frame in which the error signal was received,
(8) If no error signal is returned from the receiving device, the ERS flag is not set in SSR.
(9) If no error signal is returned from the receiving device, transmission of the frame, including
TEND
ERS
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
TDRE
ERS flag to 1 in SSR. If the RIE bit in SCR is set to the enable state, an ERI interrupt is
requested. The ERS flag should be cleared to 0 in SSR before the next parity bit sampling
timing.
indicating an error.
retransmission, is assumed to be complete, and the TEND bit is set to 1 in SSR. If the TIE bit
in SCR is set to the enable state, a TXI interrupt is requested. If TXI is enabled as a DMA
transfer activation source, the next data can be written in TDR automatically. When the
DMAC writes data in TDR, it automatically clears the TDRE bit to 0.
Transfer from TDR to TSR
Frame n
Figure 14-12 Retransmission in SCI Transmit Mode
DE
(6)
(7)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transfer from TDR to TSR
522
Retransmitted frame
(DE)
(8)
(9)
Ds
Transfer from
TDR to TSR
D0 D1 D2 D3 D4
Frame n + 1