HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 589

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HD6433044

Manufacturer Part Number
HD6433044
Description
(HD64 Series) Hitachi Single-Chip Microcomputer
Manufacturer
Hitachi Semiconductor
Datasheet

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18.5.4 RAM Control Register (RAMCR)
The RAM control register (RAMCR) enables flash-memory updates to be emulated in RAM, and
indicates flash memory errors.
Bit 7—Flash Memory Error (FLER): Indicates that an error occurred while flash memory was
being programmed or erased. When bit 7 is set, flash memory is placed in an error-protect
mode.*
Bit 7
FLER
0
1
Notes: 1. For details, see section 18.7.8, Protect Modes.
Bit
Initial value
R/W
1
2. The read data has undetermined values.
Description
Flash memory is not write/erase-protected
(is not in error protect mode*
[Clearing conditions]
Reset or hardware standby mode
Indicates that an error occurred while flash memory was being programmed or
erased, and error protection*
[Setting conditions]
Flash memory was read*
instruction fetch, but not including reading of a RAM area overlapped onto flash
memory).
A hardware exception-handling sequence (other than a reset, trace exception,
invalid instruction, trap instruction, or zero-divide exception) was executed just
before programming or erasing.
The SLEEP instruction (for transition to sleep mode or software standby mode) was
executed during programming or erasing.
A bus was released during programming or erasing.
FLER
R
7
0
6
1
2
5
1
while being programmed or erased (including vector or
1
1
)
is in effect
580
4
1
RAMS
R/W
3
0
RAM2
R/W
2
0
RAM1
R/W
1
0
(Initial value)
RAM0
R/W
0
0

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