HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 604

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HD6433044

Manufacturer Part Number
HD6433044
Description
(HD64 Series) Hitachi Single-Chip Microcomputer
Manufacturer
Hitachi Semiconductor
Datasheet

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18.7.6 Erasing Flowchart and Sample Program
Flowchart for Erasing One Block
Address + 1
No
address
Wait initial value setting x = 6.25 ms
(set bit of block to be erased to 1)
Dummy write to verify address
(flash memory latches address)
(clear bit of erased block to 0)
Write 0 data in all addresses
Clear erase block register
(
Enable watchdog timer
to be erased (prewrite)
Set erase block register
Select erase-verify mode
Set top address in block
Disable watchdog timer
V
Verify (read memory)
PP
(E bit = 1 in FLMCR)
End of block erase
Select erase mode
as verify address
OK
E
Clear
Wait (t
Wait (t
Last address?
Set
Clear EV bit
Wait (x) ms
bit = 1 in FLMCR)
Wait (z) s
(EV bit = 1)
Clear E bit
Figure 18-16 Erasing Flowchart
Start
n = 1
V
V
PP
VS1
VS2
PP
E
Yes
E
) s
) s
bit
bit
*4
*1
*2
*3
No good
595
Erasing ends
Clear erase block register
(clear bit of block to be
Clear
erased to 0)
Clear EV bit
Erase error
Notes: 1. Program all addresses to be
n
V
PP
N?
Yes
E
bit
2. Set the watchdog timer overflow
3. For the erase-verify dummy
4. Read to verify data from the
5. t
6. The erase time x is successively
erased by following the prewrite
flowchart.
interval to the value indicated in
table 18-15.
write, write H'FF using a byte
transfer instruction.
memory using a byte transfer
instruction.
z:
t
N:
incremented by the initial set
value
initial value of 6.25 ms or less
should be set, and the time for
one erasure should be 50 ms or
less.
VS1
VS2
: 4 µs
: 2 µs
5 to 10 µs
602
No
Erase-verify ends
2
n–1
Double the erase time
(n = 1, 2, 3, 4). An
(x
n + 1
n
2
5?
No
n
x)
Yes

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