HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 64

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

2.8.4 Exception-Handling Sequences
Reset Exception Handling: Reset exception handling has the highest priority. The reset state is
entered when the
changes from low to high. When reset exception handling starts the CPU fetches a start address
from the exception vector table and starts program execution from that address. All interrupts,
including NMI, are disabled during the reset exception-handling sequence and immediately after it
ends.
Interrupt Exception Handling and Trap Instruction Exception Handling: When these
exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the
program counter and condition code register on the stack. Next, if the UE bit in the system control
register (SYSCR) is set to 1, the CPU sets the I bit in the condition code register to 1. If the UE bit
is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then
the CPU fetches a start address from the exception vector table and execution branches to that
address.
Figure 2-14 shows the stack after the exception-handling sequence.
SP (ER7)
Legend
CCR:
SP:
Notes: 1.
SP–4
SP–3
SP–2
SP–1
Condition code register
Stack pointer
2.
PC is the address of the first instruction executed after the return from the
exception-handling routine.
Registers must be saved and restored by word access or longword access,
starting at an even address.
RES signal goes low. Reset exception handling starts after that, when RES
Figure 2-14 Stack Structure after Exception Handling
Before exception
handling starts
Stack area
Pushed on stack
SP (ER7)
49
SP+1
SP+2
SP+3
SP+4
After exception
handling ends
CCR
PC
Even
address