HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 640

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HD6433044

Manufacturer Part Number
HD6433044
Description
(HD64 Series) Hitachi Single-Chip Microcomputer
Manufacturer
Hitachi Semiconductor
Datasheet

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(9) Do not set or clear the VppE bit during execution of a program in flash memory.
Flash memory data cannot be read normally when the VppE bit is set or cleared. After the VppE
bit is cleared, flash memory data can be rewritten after waiting for the elapse of the Vpp enable
setup time (tVPS: 5 10 [??] µs), but flash memory cannot be accessed for purposes other than
verification (verification during programming, erasing, or prewriting). After the VppE is cleared,
wait for the elapse of the flash memory read setup time before performing program execution and
data reading in flash memory.
(10) Do not use interrupts while programming or erasing flash memory.
When Vpp is applied, disable all interrupt requests, including NMI, to give the programming or
erase operation the highest priority.
(11) The Vpp flag is set and cleared by a threshold decision on the voltage applied to the Vpp pin.
The threshold level is approximately in the range from Vcc +2 V to 11.4 V.
When this flag is set, it becomes possible to write to the flash memory control register (FLMCR)
and the erase block registers (EBR1 and EBR2), even though the Vpp voltage may not yet have
reached the programming voltage range of 12.0 V ±0.6 V. Do not actually program or erase the
flash memory until Vpp has reached the programming voltage range.
The programming voltage range for programming and erasing flash memory is 12.0 V ±0.6 V
(11.4 V to 12.6 V). Programming and erasing cannot be performed correctly outside this range.
When not programming or erasing the flash memory, ensure that the Vpp voltage does not exceed
the Vcc voltage. This will prevent unintentional programming and erasing.
(12) After the Vpp enable bit (VppE) is cleared, the flash memory read setup time (tFRS)* must
elapse before the flash memory is read.
When switching from boot mode or user program mode to normal mode (Vpp ≠ 12 V, MD? ≠ 12
V), this setup time is required as the period from VppE bit clearance until the flash memory is
read.
When switching from boot mode to another mode, a mode programming setup time (tMDS) is
required with respect to the ~RES release timing.
Note: * The flash memory read setup time stipulates the interval before flash memory is read
after the VppE bit is cleared (figure 18-30). Also, when using an external clock
(EXTAL input), after powering on and when returning from standby mode, the flash
memory read setup time must elapse before the flash memory is read.
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