HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 85

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

4.1 Overview
4.1.1 Exception Handling Types and Priority
As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur
simultaneously, they are accepted and processed in priority order. Trap instruction exceptions are
accepted at all times in the program execution state.
Table 4-1 Exception Types and Priority
Priority Exception Type
High
Low
4.1.2 Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows.
1.
2.
3.
For a reset exception, steps 2 and 3 above are carried out.
The program counter (PC) and condition code register (CCR) are pushed onto the stack.
The CCR interrupt mask bit is set to 1.
A vector address corresponding to the exception source is generated, and program execution
starts from the address indicated in that address.
Reset
Interrupt
Trap instruction (TRAPA) Started by execution of a trap instruction (TRAPA)
Section 4 Exception Handling
Start of Exception Handling
Starts immediately after a low-to-high transition at the RES pin
Interrupt requests are handled when execution of the current
instruction or handling of the current exception is completed
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