HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 859

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

D.2 Pin States at Reset
Reset in T1 State: Figure D-1 is a timing diagram for the case in which
T1 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to
the input state. AS, RD, HWR, and LWR go high, and the data bus goes to the high-impedance
state. The address bus is initialized to the low output level 0.5 state after the low level of RES is
sampled. Sampling of RES takes place at the fall of the system clock (ø).
ø
RES
Internal
reset signal
Address bus
CS
CS
AS
RD (read access)
HWR, LWR
(write access)
Data bus
(write access)
I/O port
0
7
to CS
1
Figure D-1 Reset during Memory Access (Reset during T1 State)
High
High
High
Access to external address
T1
852
T2
T3
H'000000
RES goes low during the
High impedance
High impedance
High impedance