HD64336901G Renesas Technology, HD64336901G Datasheet - Page 262
HD64336901G
Manufacturer Part Number
HD64336901G
Description
(HD64xxx Series) 16-BIT MICROCONTROLLER
Manufacturer
Renesas Technology
Datasheet
1.HD64336901G.pdf
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15.3.5
ICSR performs confirmation of interrupt request flags and status.
Rev. 1.00, 11/03, page 234 of 376
Bit Bit Name
0
Bit Bit Name
7
6
ACKBT
TDRE
TEND
I
2
C Bus Status Register (ICSR)
Initial Value R/W Description
0
Initial Value R/W Description
0
0
R/W Transmit Acknowledge
R/W Transmit Data Register Empty
R/W Transmit End
In receive mode, this bit specifies the bit to be sent at the
acknowledge timing.
0: 0 is sent at the acknowledge timing.
1: 1 is sent at the acknowledge timing.
[Setting conditions]
[Clearing conditions]
[Setting conditions]
[Clearing conditions]
When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
When TRS is set
When a start condition (including re-transfer) has been
issued
When transmit mode is entered from receive mode in
slave mode
When 0 is written in TDRE after reading TDRE = 1
When data is written to ICDRT with an instruction
When the ninth clock of SCL rises with the I
while the TDRE flag is 1
When the final bit of transmit frame is sent with the clock
synchronous serial format
When 0 is written in TEND after reading TEND = 1
When data is written to ICDRT with an instruction
2
C bus format
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