HC4053 System Logic Semiconductor, HC4053 Datasheet

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HC4053

Manufacturer Part Number
HC4053
Description
Analog Multiplexer/Demultiplexer
Manufacturer
System Logic Semiconductor
Datasheet

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Analog Multiplexer/Demultiplexer
High-Performance Silicon-Gate CMOS
fast propagation delays, low ON resistances, and low OFF leakage
currents. These analog multiplexers/demultiplexers control analog
voltages that may vary across the complete power supply range (from
V
Inputs/Outputs is to be connected, by means of an analog switch, to
the Common Output/Input.When the Enable pin is high, all analog
switches are turned off.
CMOS outputs; with pullup resistors, they are compatible with
LS/ALSTTL outputs.
SLS
CC
The SL74HC4053 utilize silicon-gate CMOS technology to achieve
The Channel-Select inputs determine which one of the Analog
The Channel-Select and Enable inputs are compatible with standard
Fast Switching and Propagation Speeds
Low Crosstalk Between Switches
Diode Protection on All Inputs/Outputs
Analog Power Supply Range (V
Digital (Control) Power Supply Range (V
Low Noise
to V
EE
System Logic
Semiconductor
).
Triple Single-Pole, Double-Position
LOGIC DIAGRAM
Plus Common Off
PIN 8 = GND
PIN 16 =V
PIN 7 = V
CC
EE
CC
-V
EE
)=2.0 to 12.0 V
CC
-GND)=2.0 to 6.0 V
X = don’t care
Enable
H
L
L
L
L
L
L
L
L
Control Inputs
T
H
H
H
H
X
C
L
L
L
L
A
FUNCTION TABLE
ORDERING INFORMATION
= -55 to 125 C for all packages
PIN ASSIGNMENT
Select
SL74HC4053N Plastic
H
H
H
H
X
B
L
L
L
L
SL74HC4053D SOIC
SL74HC4053
A
H
H
H
H
X
L
L
L
L
Z0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
Channels
None
ON
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
X0
X1
X0
X1
X0
X1
X0
X1

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HC4053 Summary of contents

Page 1

... Analog Multiplexer/Demultiplexer High-Performance Silicon-Gate CMOS The SL74HC4053 utilize silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from The Channel-Select inputs determine which one of the Analog Inputs/Outputs connected, by means of an analog switch, to the Common Output/Input ...

Page 2

... SL74HC4053 * MAXIMUM RATINGS Symbol V Positive DC Supply Voltage (Referenced to GND Negative DC Supply Voltage (Referenced to GND Analog Input Voltage IS V Digital Input Voltage (Referenced to GND Input Current Into or Out of Any Pin P Power Dissipation in Still Air, Plastic DIP+ D Tstg Storage Temperature ...

Page 3

... 6 Switch Off (Figure 6 Switch Off (Figure 6 Switch to Switch = (Figure SL74HC4053 =GND Guaranteed Limit 125 - 2.0 1.5 1.5 1.5 4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 2.0 0.3 0.3 0.3 4.5 0.9 0.9 0.9 6.0 1.2 1.2 1.2 6.0 0.1 1.0 1.0 6 ...

Page 4

... SL74HC4053 AC ELECTRICAL CHARACTERISTICS Symbol Parameter Maximum Propagation Delay, Channel-Select to PLH PHL Analog Output (Figures 8 and Maximum Propagation Delay , Analog Input to PLH PHL Analog Output (Figures 10 and 11 Maximum Propagation Delay , Enable to Analog PLZ PHZ Output (Figures 12 and 13 Maximum Propagation Delay , Enable to Analog ...

Page 5

... C = MHz kHz THD Measured Source V =4.0 V sine wave =8.0 V sine wave =11.0 V sine wave IS PP SL74HC4053 (GND = 0 Limit 2.25 -2.25 120 4.50 -4.50 120 6.00 -6.00 120 2.25 -2.25 -50 IS 4.50 -4.50 -50 6.00 -6.00 -50 2.25 -2.25 -40 4.50 -4 ...

Page 6

... SL74HC4053 Figure 2. Maximum Off Channel Leakage Current, Any One Channel, Test Set-U Figure 4. Maximum On Channel Leakage Current, Channel to Channel, Test Set-U * Includes all probe and jig capacitance. Figure 6. Off Channel Feedthrough Isolation, Test Set-U P Figure 1. On Resistance Test Set-Up Figure 3. Maximum Off Channel Leakage Current, ...

Page 7

... Figure 8. Swi tching Weveforms Figure 10. Switching Weveforms Figure 12. Switching Weveforms System Logic SLS Semiconductor SL74HC4053 * Includes all probe and jig capacitance. Figure 9. Test Set-U , Channel Select to Analog Out P * Includes all probe and jig capacitance. Figure 11. Test Set-U , Analog In to Analog Out P Figure 13 ...

Page 8

... SL74HC4053 * Includes all probe and jig capacitance. Figure 14. Crosstalk Between Any Two Switches, Test Set-U p Figure 16. Total Harmonic Distortion, Test Set-U Figure 15. Power Dissipation Capacitance, Test Set-U EXPANDED LOGIC DIAGRAM p P System Logic SLS Semiconductor ...

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