M58BW016BB ST Microelectronics, M58BW016BB Datasheet - Page 16

• Manufacturer Part Number: M58BW016BB
• Description: 16 Mbit 512Kb x32 / Boot Block / Burst 3V Supply Flash Memories
• Manufacturer: ST Microelectronics

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
the Address Inputs and pulsing Latch Enable Low,
V
mand Interface on the rising edge of Latch Enable,
Write Enable or Chip Enable, whichever occurs
first. Commands and Input Data are latched on the
rising edge of Chip Enable, E, or Write Enable, W,
whichever occurs first. Output Enable must remain
High, and Output Disable Low, during the whole
Asynchronous Bus Write operation.
See Figure 13, Asynchronous Latch Controlled
Write AC Waveforms, and Table 19, Asynchro-
nous Write and Latch Controlled Write AC Charac-
teristics, for details of the timing requirements.
Output Disable. The data outputs are high im-
pedance when the Output Enable, G, is at V
Output Disable, GD, is at V
Standby. When Chip Enable is High, V
Program/Erase Controller is idle, the memory en-
ters Standby mode, the power consumption is re-
duced to the standby level and the Data Inputs/
Outputs pins are placed in the high impedance
state regardless of Output Enable, Write Enable or
Output Disable inputs.
Automatic Low Power. If there is no change in
the state of the bus for a short period of time during
Asynchronous Bus Read operations the memory
Table 4. Asynchronous Bus Operations
Note: X = Don’t Care
16/63
Asynchronous Bus Read
Asynchronous Latch
Controlled Bus Read
Asynchronous Page
Read
Asynchronous Bus Write
Asynchronous Latch
Controlled Bus Write
Output Disable, G
Output Disable, GD
Standby
Reset/Power-Down
IL
. The Address Inputs are latched by the Com-
Bus Operation
Address Latch
Read
Address Latch
Write
IL
.
Step
IH
V
V
V
V
V
V
V
V
V
V
, and the
E
X
IH
IL
IL
IL
IL
IL
IL
IL
IL
IL
IH
V
V
V
V
V
V
V
V
V
or
G
X
X
IH
IH
IH
IH
IL
IL
IL
IL
IL
GD
V
V
V
V
V
V
V
X
X
X
X
enters Auto Low Power mode where the internal
Supply Current is reduced to the Auto-Standby
Supply Current. The Data Inputs/Outputs will still
output data if a Bus Read operation is in progress.
Automatic Low Power is only available in Asyn-
chronous Read modes.
Power-Down. The memory is in Power-down
when Reset/Power-Down, RP, is at V
er consumption is reduced to the power-down lev-
el
independent of the Chip Enable, E, Output Enable,
G, Output Disable, GD, or Write Enable, W, inputs.
Electronic Signature. Two codes identifying the
manufacturer and the device can be read from the
memory allowing programming equipment or ap-
plications to automatically match their interface to
the characteristics of the memory. The Electronic
Signature is output by giving the Read Electronic
Signature command. The manufacturer code is
output when all the Address inputs are at V
device code is output when A1 is at V
other address pins are at V
a Read Memory Array command to return to Read
mode.
IH
IH
IH
IH
IH
IH
IL
and
V
V
V
V
V
V
V
V
V
W
X
X
IH
IH
IH
IH
IH
IH
IL
IL
IL
the
V
V
V
V
V
V
V
V
V
V
RP
V
IH
IH
IH
IH
IH
IH
IH
IH
IH
IH
IL
outputs
V
V
V
V
V
V
L
X
X
X
X
X
IH
IH
IL
IL
IL
IL
are
Address
Address
Address
Address
Address
A0-A18
IL
X
X
X
X
X
X
. See Table 5. Issue
high
IH
Data Output
Data Output
Data Output
IL
DQ0-DQ31
impedance,
Data Input
Data Input
. The pow-
and all the
High Z
High Z
High Z
High Z
High Z
High Z
IL
. The