TE28F008B3xxx Intel, TE28F008B3xxx Datasheet
TE28F008B3xxx
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TE28F008B3xxx Summary of contents
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... Extended Temperature Operation –40 °C to +85 °C The Smart 3 Advanced Boot Block, manufactured on Intel’s latest 0.25 µ technology, represents a feature- rich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage capability (2.7 V read, program and erase) with high-speed, low-power operation. Several new features have been added, including the ability to drive the I ...
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... Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. ...
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... Program and Erase Timings .......................31 5.0 RESET OPERATIONS ..................................33 6.0 ORDERING INFORMATION..........................34 7.0 ADDITIONAL INFORMATION .......................36 APPENDIX A: Write State Machine Current/Next States.....................................37 APPENDIX B: Access Time vs. Capacitive Load...........................................38 APPENDIX C: Architecture Block Diagram ......39 APPENDIX D: Word-Wide Memory Map Diagrams......................................................40 APPENDIX E: Byte Wide Memory Map Diagrams......................................................43 APPENDIX F: Program and Erase Flowcharts .45 PAGE 3 ...
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SMART 3 ADVANCED BOOT BLOCK REVISION HISTORY Number -001 Original version Section 3.4, V Program and Erase Voltages , added -002 PP Updated Figure 9: Automated Block Erase Flowchart Updated Figure 10: Erase Suspend/Resume Flowchart (added program to table) Updated ...
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... V” refers to the full voltage range 2.7 V–3.6 V (except where noted otherwise) and “ V” refers ±5%. Section 1.0 and PP 2.0 provide an overview of the flash memory family including applications, pinouts and pin descriptions. Section 3.0 describes the memory organization and operation for these products. Sections 4.0 and 5.0 contain ...
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... SMART 3 ADVANCED BOOT BLOCK 1.2 Product Overview Intel provides the most flexible voltage solution in the flash industry, providing three discrete voltage supply pins: V for read operation CCQ swing, and V for program and erase operation. All PP Smart 3 Advanced Boot Block flash memory products provide program/erase capability at 2 ...
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WE ...
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SMART 3 ADVANCED BOOT BLOCK WE CCQ 11 F GND D ...
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WE CCQ 15 F GND NOTES: 1. ...
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... OUTPUT ENABLE: Enables the device’s outputs through the data buffers during a read operation. OE# is active low. WE# INPUT WRITE ENABLE: Controls writes to the Command Register and memory array. WE# is active low. Addresses and data are latched on the rising edge of the second WE# pulse. RP# ...
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... For the address locations of each block, see the memory maps in Appendix D. 2.2.1 PARAMETER BLOCKS The Smart 3 Advanced Boot Block flash memory architecture includes parameter blocks to facilitate storage of frequently updated small parameters (e.g., data that would normally be stored in an EEPROM). By using software techniques, the word- rewrite functionality of EEPROMs can be emulated ...
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... Smart 3 Advanced Boot Block flash memory devices read, program and erase in-system via the disable local CPU or microcontroller. All bus cycles to or from the flash memory conform to standard microcontroller bus cycles. Four control pins dictate the data flow in and out of the flash component: are CE#, OE#, WE# and RP# ...
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... CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel’s Flash memories allow proper CPU initialization following a system reset power through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU ...
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... Table 4. comprehensive chart showing the state transitions is in Appendix A. Table 4. Command Codes and Descriptions Code Device Mode 00, Unassigned commands that should not be used. Intel reserves the right to 01, Invalid/ redefine these codes for future functions. 60, Reserved 2F, C0 Read Array Places the device in read array mode, such that array data will be output on the data pins ...
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... Issuing this command clears those bits to “0.” 90 Read Identifier Puts the device into the intelligent identifier read mode, so that reading the device will output the manufacturer and device codes ( for device, all other address inputs must be 0). See Section 3.2.2. ...
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... Verify the bits are sufficiently programmed. Programming the memory results in specific bits within an address location being changed to a “0.” If the user attempts to program “1”s, the memory cell contents do not – change and no error occurs ...
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... Since an erase operation requires on the order of seconds to complete, an Erase Suspend command is provided to allow erase-sequence interruption in order to read data from or program data to another block in memory. Once the erase sequence is IH. started, writing the Erase Suspend command to the CUI requests that the WSM pause the erase sequence at a predetermined point in the erase algorithm ...
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... PD: Program Data IA: Identifier Address ID: Identifier Data 1. Bus operations are defined in Table 3. 2. Following the Intelligent Identifier command, two read operations access manufacturer and device codes. A manufacturer code for device code Either 40H or 10H command is valid although the standard is 40H. ...
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Table 7. Status Register Bit Definition WSMS ESS SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = ERASE-SUSPEND STATUS (ESS Erase Suspended 0 = Erase In Progress/Completed SR.5 ...
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... Power Consumption Intel® Flash devices have a tiered approach to power savings that can significantly reduce overall system power consumption. The Automatic Power Savings (APS) feature reduces power consumption when the device is selected but idle ...
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... If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Intel recommends connecting RP# to the system CPU RESET# signal to allow proper CPU/flash initialization following system reset. ...
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... V ), the CUI must be reset to read array mode PPLK via the Read Array command if access to the flash memory array is desired. 3.7 Power Supply Decoupling Flash memory’s power switching characteristics require careful device decoupling. designers should consider three supply current issues: 1. Standby current levels (I ...
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... NOTICE: This datasheet contains preliminary information on new products in production. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. * WARNING: Stressing the device beyond the "Absolute Maximum Ratings" ...
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SMART 3 ADVANCED BOOT BLOCK 4.2 Operating Conditions Symbol Parameter T Operating Temperature Supply Voltage CC CC1 V CC2 V CC3 V I/O Supply Voltage CCQ1 V CCQ2 V CCQ3 V Program and Erase Voltage PP1 V ...
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DC Characteristics V 2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3 2.7 V–3.6 V 1.65 V–2.5 V 1.8 V–2.5 V CCQ Sym Parameter Note Typ I Input Load Current Output Leakage 6 ...
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SMART 3 ADVANCED BOOT BLOCK 4.4 DC Characteristics (Continued) V 2.7 V–3 2.7 V–3.6 V CCQ Sym Parameter Note Min V Input Low Voltage –0 Input High Voltage CCQ IH –0.4V V Output Low ...
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V CCQ V CCQ INPUT 2 0.0 NOTE: AC test inputs are driven at V for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output timing ends CCQ Input rise and fall times ...
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SMART 3 ADVANCED BOOT BLOCK 4.5 AC Characteristics —Read Operations Product 3.0 V–3.6 V 2.7 V–3 Sym Parameter Note R1 t Read Cycle Time AVAV R2 t Address to AVQV Output Delay R3 t CE# to Output 2 ...
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Device and Address Selection V IH ADDRESSES (A) Address Stable CE# ( OE# ( WE# ( High Z DATA (D/ ...
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SMART 3 ADVANCED BOOT BLOCK 4.6 AC Characteristics —Write Operations Product # Symbol Parameter RP# High Recovery to WE# PHWL (CE#) Going Low t PHEL CE# (WE#) Setup to WE# ELWL (CE#) Going Low ...
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Program and Erase Timings Symbol Parameter t 8-KB Parameter Block BWPB Program Time (Byte) 4-KW Parameter Block Program Time (Word) t 64-KB Main Block BWMB Program Time (Byte) 32-KW Main Block Program Time(Word WHQV1 EHQV1 Byte ...
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SMART 3 ADVANCED BOOT BLOCK ADDRESSES [ CE#(WE#) [E(W OE# [ WE#(CE#) [W(E High Z DATA [D/Q] ...
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RESET OPERATIONS RP# (P) (A) Reset during Read Mode RP# (P) (B) Reset during Program or Block Erase, RP# (P) (C) Reset Program or Block Erase, Figure 9. AC Waveform: Deep Power-Down/Reset Operation Symbol Parameter t RP# Low to ...
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... ORDERING INFORMATION Package TE = 40-Lead/48-Lead TSOP GT = 48-Ball µBGA* CSP Product line designator for all Intel Flash products Device Density 320 = x16 (32 Mbit) 160 = x16 (16 Mbit) 800 = x16 (8 Mbit) 400 = Mbit) 032 = x 8 (32 Mbit) ...
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... Product can be ordered in either 0.25 µm or 0.4 µm material. The “A” before the access speed specifies 0.25 µm material. 4. For new designs, Intel recommends using 0.25 µm Advanced Boot Block devices. PRELIMINARY SMART 3 ADVANCED BOOT BLOCK 48-Ball µBGA* ...
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... FDI Interactive: Play with Intel’s Flash Data Integrator on Your PC NOTE: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.Intel.com or http://developer.intel.com for technical documentation and tools ...
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APPENDIX A WRITE STATE MACHINE CURRENT/NEXT STATES Current SR.7 Data Read Program State When Array Setup Read (FFH) (10/40H) Read Array “1” Array Read Program Array Setup Read Status “1” Status Read Program Array Setup Read “1” Identifier Read Program ...
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SMART 3 ADVANCED BOOT BLOCK ACCESS TIME VS. CAPACITIVE LOAD Access Time vs. Load Capacitance Load Capacitance (pF) This chart shows a derating curve for device access time with respect ...
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APPENDIX C ARCHITECTURE BLOCK DIAGRAM V CCQ Output Buffer Power Reduction Control Y-Decoder Input Buffer Address Latch X-Decoder Address Counter PRELIMINARY SMART 3 ADVANCED BOOT BLOCK DQ - Input Buffer Identifier Register Status Register ...
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... SMART 3 ADVANCED BOOT BLOCK WORD-WIDE MEMORY MAP DIAGRAMS 8-Mbit, 16-Mbit, and 32-Mbit Word-Wide Memory Addressing Top Boot Size 8M 16M (KW) 4 7F000-7FFFF FF000-FFFFF 1FF000-1FFFFF 4 7E000-7EFFF FE000-FEFFF 1FE000-1FEFFF 4 7D000-7DFFF FD000-FDFFF 1FD000-1FDFFF 4 7C000-7CFFF FC000-FCFFF 1FC000-1FCFFF 4 7B000-7BFFF FB000-FBFFF 1FB000-1FBFFF 4 7A000-7AFFF FA000-FAFFF 1FA000-1FAFFF 4 79000-79FFF F9000-F9FFF 1F9000-1F9FFF ...
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... Word-Wide Memory Addressing (Continued) Top Boot Size 8M 16M (KW) 32 0F8000-0FFFFF 32 0F0000-0F7FFF 32 0E8000-0EFFFF 32 0E0000-0E7FFF 32 0D8000-0DFFFF 32 0D0000-0D7FFF 32 0C8000-0CFFFF 32 0C0000-0C7FFF 32 0B8000-0BFFFF 32 0B0000-0B7FFF 32 0A8000-0AFFFF 32 0A0000-0A7FFF 32 098000-09FFFF 32 090000-097FFF 32 088000-08FFFF 32 080000-087FFF 32 078000-07FFFF 32 070000-077FFF 32 068000-06FFFF 32 060000-067FFF 32 058000-05FFFF 32 050000-057FFF 32 048000-04FFFF 32 040000-047FFF 32 038000-03FFFF 32 030000-037FFF 32 028000-02FFFF 32 020000-027FFF ...
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... SMART 3 ADVANCED BOOT BLOCK 4-Mbit Word-Wide Memory Addressing Top Boot Size (KW 30000-037FFF 10000-017FFF Bottom Boot 4M Size (KW) 3F000-3FFFF 32 3E000-3EFFF 32 3D000-3DFFF 32 3C000-3CFFF 32 3B000-3BFFF 32 3A000-3AFFF 32 39000-39FFF 32 38000-38FFF 4 4 28000-2FFFF 4 20000-2FFFF 4 18000-1FFFF 4 4 08000-0FFFF 4 00000-07FFF 4 PRELIMINARY 4M 38000-3FFFF ...
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... APPENDIX E BYTE-WIDE MEMORY MAP DIAGRAMS Byte-Wide Memory Addressing Top Boot Size 8M 16M (KB) 8 FE000-FFFFF 1FE000-1FFFFF 3FE000-3FFFFF 8 FC000-FDFFF 1FC000-1FDFFF 3FC000-3FDFFF 8 FA000-FBFFF 1FA000-1FBFFF 3FA000-3FBFFF 8 F8000-F9FFF 1F8000-1F9FFF 3F8000-3F9FFF 8 F6000-F7FFF 1F6000-1F7FFF 3F6000-3F7FFF 8 F4000-F5FFF 1F4000-1F5FFF 3F4000-3F5FFF 8 F2000-F3FFF 1F2000-1F3FFF 3F2000-3F3FFF 8 F0000-F1FFF 1F0000-1F1FFF 3F0000-3F1FFF 64 E0000-EFFFF 1E0000-1EFFFF 3E0000-3EFFFF 64 D0000-DFFFF ...
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... SMART 3 ADVANCED BOOT BLOCK Byte-Wide Memory Addressing (Continued) Top Boot Size 8M 16M (KB) 64 1F0000-1FFFFF 64 1E0000-1EFFFF 64 1D0000-1DFFFF 64 1C0000-1CFFFF 64 1B0000-1BFFFF 64 1A0000-1AFFFF 64 190000-19FFFF 64 180000-18FFFF 64 170000-17FFFF 64 160000-16FFFF 64 150000-15FFFF 64 140000-14FFFF 64 130000-13FFFF 64 120000-12FFFF 64 110000-11FFFF 64 100000-10FFFF 64 0F0000-0FFFFF 64 0E0000-0EFFFF 64 0D0000-0DFFFF 64 0C0000-0CFFFF 64 0B0000-0BFFFF 64 0A0000-0AFFFF 64 090000-09FFFF 64 080000-08FFFF 64 070000-07FFFF 64 060000-06FFFF 64 050000-05FFFF 64 040000-04FFFF ...
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APPENDIX F PROGRAM AND ERASE FLOWCHARTS Start Write 40H Program Address/Data Read Status Register No SR Yes Full Status Check if Desired Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above ...
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SMART 3 ADVANCED BOOT BLOCK Start Write B0H Write 70H Read Status Register 0 SR SR.2 = Program Completed 1 Write FFH Read Array Data No Done Reading Yes Write D0H Write FFH Program Resumed Read Array ...
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Start Write 20H Write D0H and Block Address Read Status Register Suspend Erase Loop No 0 Yes SR.7 = Suspend Erase 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) ...
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SMART 3 ADVANCED BOOT BLOCK Start Write B0H Write 70H Read Status Register 0 SR SR.6 = Erase Completed 1 Write FFH Read Array Data No Done Reading Yes Write D0H Write FFH Erase Resumed Read Array ...