M36DR432BD ST Microelectronics, M36DR432BD Datasheet - Page 9
M36DR432BD
Manufacturer Part Number
M36DR432BD
Description
32 Mbit 2Mb x16 / Dual Bank / Page Flash Memory and 4 Mbit 256Kb x16 SRAM / Multiple Memory Product
Manufacturer
ST Microelectronics
Datasheet
1.M36DR432BD.pdf
(52 pages)
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the memory and reduces the power consumption
to the standby level. ES can also be used to con-
trol writing to the SRAM memory array, while WS
remains at V
ES at V
SRAM Write Enable (WS). The Write Enable in-
put controls writing to the SRAM memory array.
WS is active Low.
SRAM Output Enable (GS). The Output Enable
gates the outputs through the data buffers during
a read operation of the SRAM chip. GS is active
Low.
IL
at the same time.
IL
. It is not allowed to set EF at V
IL
and
SRAM Upper Byte Enable (UBS). Enables
upper bytes for SRAM (DQ8-DQ15). UBS is active
Low.
SRAM Lower Byte Enable (LBS). Enables the
lower bytes for SRAM (DQ0-DQ7). LBS is active
Low.
V
SRAM power supply for all operations.
Note: Each device in a system should have
V
tor close to the pin. See Figure 7, AC Measure-
ment Load Circuit. The PCB trace widths
should be sufficient to carry the required V
program and erase currents.
DDS
DDF
Supply Voltage (1.65V to 2.2V). V
and V
PPF
M36DR432AD, M36DR432BD
decoupled with a 0.1µF capaci-
DDS
is the
9/52
PPF
the
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