Z8F160x Zilog, Z8F160x Datasheet - Page 122
Z8F160x
Manufacturer Part Number
Z8F160x
Description
Z8 Encore / Microcontrollers with Flash Memory and 10 Bit A/D Converter
Manufacturer
Zilog
Datasheet
1.Z8F160X.pdf
(246 pages)
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PS017610-0404
Input Sample Time
Multi-Master Operation
(CLKPOL = 0)
(CLKPOL = 1)
Figure 78. SPI Timing When
In a multi-master SPI system, all SCK pins are tied together, all MOSI pins are tied
together and all MISO pins are tied together. All SPI pins must then be configured in
open-drain mode to prevent bus contention. At any one time, only one SPI device is con-
figured as the Master and all other SPI devices on the bus are configured as Slaves. The
Master enables a single Slave by asserting the SS pin on that Slave only. Then, the single
Master drives data out its SCK and MOSI pins to the SCK and MOSI pins on the Slaves
(including those which are not enabled). The enabled Slave drives data out its MISO pin to
the MISO Master pin.
For a Master device operating in a multi-master system, if the SS pin is configured as an
input and is driven Low by another Master, the COL bit is set to 1 in the SPI Status Regis-
ter. The COL bit indicates the occurrence of a multi-master collision (mode fault error con-
dition).
MOSI
MISO
SCK
SCK
SS
Bit7
Bit7
Bit6
Bit6
PHASE
Bit5
Bit5
is 1
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Bit4
Bit4
Bit3
Bit3
Bit2
Bit2
Serial Peripheral Interface
Bit1
Bit1
Bit0
Bit0
Z8 Encore!
®
104
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