MC9328MXL ETC, MC9328MXL Datasheet

Page 1

... The new MC9328MXL features the advanced and power- efficient ARM920T™ core that operates at speeds up to 200 MHz. Integrated modules, which include an LCD controller, USB support, and an MMC/SD host controller, support a suite of peripherals to enhance any product seeking to provide a rich multimedia experience ...

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... SPI 2 UART 1 UART 2 SSI USB Device Figure 1. MC9328MXL Functional Block Diagram 1.1 Conventions This document uses the following conventions: • OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET. • Logic level one is a voltage that corresponds to Boolean true (1) state. ...

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... Features To support a wide variety of applications, the MC9328MXL offers a robust array of features, including the following: • ARM920T™ Microprocessor Core • AHB to IP Bus Interfaces (AIPIs) • External Interface Module (EIM) • SDRAM Controller (SDRAMC) • DPLL Clock and Power Control Module • ...

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... Requirements” on page 12 1.5 Product Documentation The following documents are required for a complete description of the MC9328MXL and are necessary to design properly with the device. Especially for those not familiar with the ARM920T processor or previous DragonBall products, the following documents are helpful when used in conjunction with this document. ...

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... Table 2 provides ordering information for both the 256-lead mold array process ball grid array (MAPBGA) package and the 225-lead BGA package. Package Type Frequency 256-lead MAPBGA 150 MHz 200 MHz 225-lead MAPBGA 150 MHz 200 MHz Freescale Semiconductor Table 2. MC9328MXL Ordering Information Temperature Solderball Type Standard - Pb-free O ...

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... Signals and Connections 2 Signals and Connections Table 3 identifies and describes the MC9328MXL signals that are assigned to package pins. The signals are grouped by the internal module that they are connected to. Signal Name A[24:0] Address bus signals D[31:0] Data bus signals EB0 MSB Byte Strobe—Active low external enable byte signal that controls D [31:24]. ...

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... Table 3. MC9328MXL Signal Descriptions (Continued) Signal Name CSD1 SDRAM/SyncFlash Chip-select signal which is multiplexed with CS3 signal. These two signals are selectable by programming the system control register. By default, CSD1 is selected can be used as SyncFlash boot chip-select by properly configuring BOOT [3:0] input pins. RAS ...

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... SPI2 Master TxData Output—This signal is multiplexed with a GPI/O pin yet shows primary or alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin. ...

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... SPI2 Serial Clock—This signal is multiplexed with a GPI/O pin yet shows primary or alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin. ...

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... Signals and Connections Table 3. MC9328MXL Signal Descriptions (Continued) Signal Name UART1_RTS Request to Send UART1_CTS Clear to Send UART2_RXD Receive Data UART2_TXD Transmit Data UART2_RTS Request to Send UART2_CTS Clear to Send UART2_DSR Data Set Ready UART2_RI Ring Indicator UART2_DCD Data Carrier Detect UART2_DTR Data Terminal Ready Serial Audio Port – ...

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... Supply routed through substrate of package; not to be bonded SGND Ground routed through substrate of package; not to be bonded 3 Specifications This section contains the electrical specifications and timing diagrams for the MC9328MXL processor. 3.1 Maximum Ratings Table 4 provides information on maximum ratings. Rating Supply voltage ...

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... Specifications 3.2 Recommended Operating Range Table 5 provides the recommended operating ranges for the supply voltages. The MC9328MXL has multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for internal logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of VDD and VSS provides power to the enclosed I/ O pads ...

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... Parameter EXTAL32k input jitter (peak to peak) Freescale Semiconductor Parameter ° 2.0 mA -2.5 mA) = 1.8V Table 7. Tristate Signal Timing Parameter Table 8. 32k/16M Oscillator Signal Timing Minimum – MC9328MXL Advance Information, Rev. 5 Specifications Min Typical Max – 60 – 0.7V – Vdd+0.2 DD – – 0.4 0.7V – Vdd DD – ...

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... TBD Valid Data 4a Figure 2. Trace Port Timing Diagram 1.8V ± 0.10V Minimum Maximum 0 85 1.3 – 3 – MC9328MXL Advance Information, Rev. 5 RMS Maximum Unit – – ms TBD TBD – – – – 1 Valid Data 4b 3.0V ± 0.30V Unit Minimum Maximum ...

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... No. 3a Clock rise time 3b Clock fall time 4a Output hold time 4b Output setup time Freescale Semiconductor 1.8V ± 0.10V Minimum Maximum – 4 – 3 2.28 – 3.42 – MC9328MXL Advance Information, Rev. 5 Specifications 3.0V ± 0.30V Unit Minimum Maximum – – – – ...

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... FPL mode and integer MF (does not include pre-multi lock-in time) FPL mode and integer MF (does not include pre-multi lock-in time) – Integer MF, FPL mode, Vcc=1.8V – FOL mode, integer MF 200 MHz, Vcc = 1.8V dck MC9328MXL Advance Information, Rev. 5 Minimum Typical Maximum 5 – 100 5 – – ...

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... Be aware that NVDD must ramp least 1.8V before QVDD is powered up to prevent forward biasing. 90% AVDD POR RESET_POR RESET_DRAM HRESET RESET_OUT CLK32 HCLK Freescale Semiconductor NOTE: 1 10% AVDD 2 Exact 300ms Figure 3. Timing Relationship with POR MC9328MXL Advance Information, Rev. 5 Specifications 3 7 cycles @ CLK32 4 14 cycles @ CLK32 17 ...

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... If an external stable clock source (already running) is used instead of a crystal, the width of POR should be ignored in calculating timing for the start-up process 1.8V ± 0.10V Min 1 note 300 MC9328MXL Advance Information, Rev cycles @ CLK32 4 3.0V ± 0.30V Unit Max Min Max – 1 – – note ...

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... External Interface Module The External Interface Module (EIM) handles the interface to devices external to the MC9328MXL, including the generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in Figure 5, and Table 12 on page 20 defines the parameters of signals. (HCLK) Bus Clock ...

Page 20

... Clock refers to the system clock signal, HCLK, generated from the System PLL 20 Table 12. EIM Bus Timing Parameter Table 1.8V ± 0.10V Min Typical 2.48 3.31 1.55 2.48 2.69 3.31 1.55 2.48 1.35 2.79 1.86 2.59 2.32 2.62 2.11 2.52 2.38 2.69 2.17 2.59 1.91 2.52 1.81 2.42 1.97 2.59 1.76 2.48 2.07 2.79 1.97 2.79 1.91 2.62 1.61 2.62 1.61 2.62 1.55 2.48 1.55 2.59 5.54 – 0 – 1.81 2.72 1.45 2.48 1.63 – 2.52 – MC9328MXL Advance Information, Rev. 5 3.0V ± 0.30V Unit Max Min Typical Max 9.11 2.4 3.2 8.8 ns 5.69 1.5 2.4 5.5 ns 7.87 2.6 3.2 7.6 ns 6.31 1.5 2.4 6.1 ns 6.52 1.3 2.7 6.3 ns 6.11 1.8 2.5 5.9 ns 6.85 2.3 2.6 6.8 ns 6.55 2.1 2.5 6.5 ns 7.04 2.3 2.6 6.8 ns 6.73 2.1 2.5 6.5 ns 5.54 1.9 2.5 5 ...

Page 21

... The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state. Freescale Semiconductor Table 13. Access Cycle Timing Parameters 1.8V ± 0.10V Min – MC9328MXL Advance Information, Rev. 5 Specifications 3.0V ± 0.30V Unit Max Min Max T – T – 0 – ...

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... T is the system clock period (system clock is 96 MHz). 3. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state Table 14. Access Cycle Timing Parameters 1.8V ± 0.10V Min 0 MC9328MXL Advance Information, Rev. 5 3.0V ± 0.30V Unit Max Min Max – 0 – ...

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... Seq/Nonseq hwrite haddr hready weim_hrdata weim_hready weim_bclk weim_addr Last Valid Address weim_cs weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_data_in Freescale Semiconductor Read V1 Last Valid Data Read Figure 8. WSC = 1, A.HALF/E.HALF MC9328MXL Advance Information, Rev. 5 Specifications ...

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... Last Valid Data weim_hrdata weim_hready weim_bclk weim_addr Last Valid Address weim_cs[0] weim_r/w weim_lba weim_oe weim_eb weim_data_out Figure 9. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF 24 V1 Write Data (V1) Last Valid Data Last Valid Data MC9328MXL Advance Information, Rev. 5 Unknown V1 Write Write Data (V1) Freescale Semiconductor ...

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... Last Valid Addr weim_cs[0] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_data_in Figure 10. WSC = 1, OEA = 1, A.WORD/E.HALF Freescale Semiconductor Read V1 Last Valid Data Address V1 Read 1/2 Half Word MC9328MXL Advance Information, Rev. 5 Specifications V1 Word Address 2/2 Half Word 25 ...

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... Last Valid Data weim_hrdata weim_hready weim_bclk weim_addr Last Valid Addr weim_cs[0] weim_r/w weim_lba weim_oe weim_eb weim_data_out Figure 11. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF 26 Write Data (V1 Word) Last Valid Data Address V1 1/2 Half Word MC9328MXL Advance Information, Rev. 5 Address Write 2/2 Half Word Freescale Semiconductor ...

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... Last Valid Addr weim_cs[3] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_data_in Figure 12. WSC = 3, OEA = 2, A.WORD/E.HALF Freescale Semiconductor Last Valid Data Address V1 Read 1/2 Half Word MC9328MXL Advance Information, Rev. 5 Specifications V1 Word Address 2/2 Half Word 27 ...

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... Last Valid Addr weim_cs[3] weim_r/w weim_lba weim_oe weim_eb weim_data_out] Last Valid Data Figure 13. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF 28 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXL Advance Information, Rev. 5 Address 2/2 Half Word Freescale Semiconductor ...

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... Last Valid Addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_data_in Figure 14. WSC = 3, OEA = 4, A.WORD/E.HALF Freescale Semiconductor Last Valid Data Address V1 Read 1/2 Half Word MC9328MXL Advance Information, Rev. 5 Specifications V1 Word Address 2/2 Half Word 29 ...

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... Last Valid Addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb weim_data_out Last Valid Data Figure 15. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF 30 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXL Advance Information, Rev. 5 Address 2/2 Half Word Freescale Semiconductor ...

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... Last Valid Addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_data_in Figure 16. WSC = 3, OEN = 2, A.WORD/E.HALF Freescale Semiconductor Last Valid Data Address V1 Read 1/2 Half Word MC9328MXL Advance Information, Rev. 5 Specifications V1 Word Address 2/2 Half Word 31 ...

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... Last Valid Addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_data_in Figure 17. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF 32 Last Valid Data Address V1 Read 1/2 Half Word MC9328MXL Advance Information, Rev Word Address 2/2 Half Word Freescale Semiconductor ...

Page 33

... Last Valid Addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb weim_data_out Last Valid Data Figure 18. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF Freescale Semiconductor Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXL Advance Information, Rev. 5 Specifications Unknown Address 2/2 Half Word 33 ...

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... Last Valid Addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb weim_data_out Last Valid Data Figure 19. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF 34 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXL Advance Information, Rev. 5 Unknown Address 2/2 Half Word Freescale Semiconductor ...

Page 35

... Figure 20. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF Freescale Semiconductor Nonseq Write V8 Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MXL Advance Information, Rev. 5 Specifications Write Data Read Data Address V8 Write Write Data 35 ...

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... Figure 21. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF 36 Read Idle Nonseq Write V8 Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MXL Advance Information, Rev. 5 Write Write Data Read Data Address V8 Write Write Data Freescale Semiconductor ...

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... Last Valid Addr weim_cs weim_r/w weim_lba weim_oe weim_eb weim_data_out Last Valid Data Figure 22. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF Freescale Semiconductor Write Data (Word) Last Valid Data Address V1 Write Write Data (1/2 Half Word) MC9328MXL Advance Information, Rev. 5 Specifications Address Write Data (2/2 Half Word) 37 ...

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... Figure 23. WSC = 3, CSA = 1, A.HALF/E.HALF 38 Nonseq Write V8 Last Valid Data Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MXL Advance Information, Rev. 5 Write Data Read Data Address V8 Write Write Data Freescale Semiconductor ...

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... Last Valid weim_cs[4] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_data_in Figure 24. WSC = 2, OEA = 2, CNC = 3, BCM = 0, A.HALF/E.HALF Freescale Semiconductor Idle Seq Read V2 Read Data (V1) Address V1 CNC Read Read Data (V1) MC9328MXL Advance Information, Rev. 5 Specifications Read Data (V2) Address V2 Read Data (V2) 39 ...

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... Figure 25. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF 40 Idle Nonseq Write V8 Last Valid Data Address V1 CNC Read Read Data Last Valid Data MC9328MXL Advance Information, Rev. 5 Write Data Read Data Address V8 Write Write Data Freescale Semiconductor ...

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... Last Valid Addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_ecb weim_data_in Figure 26. WSC = 3, SYNC = 1, A.HALF/E.HALF Freescale Semiconductor Nonse Read V5 Address V1 Read V1 Word V2 Word MC9328MXL Advance Information, Rev. 5 Specifications Idle Address V5 V5 Word V6 Word 41 ...

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... Figure 27. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD 42 Seq Seq Read Read Word V2 Word Address V1 Read V1 Word V2 Word MC9328MXL Advance Information, Rev. 5 Idle Seq Read V4 V3 Word V4 Word V3 Word V4 Word Freescale Semiconductor ...

Page 43

... Last Valid Data weim_hready weim_bclk weim_addr Last Valid weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_ecb weim_data_in Figure 28. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF Freescale Semiconductor Seq Read V2 V1 Word Address V1 Read V1 1/2 V1 2/2 MC9328MXL Advance Information, Rev. 5 Specifications Idle V2 Word Address V2 V2 1/2 V2 2/2 43 ...

Page 44

... Last weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_ecb weim_data_in Figure 29. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF 44 Last Valid Data Address V1 Read V1 1/2 MC9328MXL Advance Information, Rev. 5 Idle Seq Read V2 V1 Word V2 Word V1 2/2 V2 1/2 V2 2/2 Freescale Semiconductor ...

Page 45

... Last weim_addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_ecb weim_data_in Figure 30. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF Freescale Semiconductor Last Valid Data Address V1 Read V1 1/2 MC9328MXL Advance Information, Rev. 5 Specifications Idle Seq Read V2 V1 Word V2 Word V1 2/2 V2 1/2 V2 2/2 45 ...

Page 46

... Figure 32. Master SPI Timing Diagram Using SPI_RDY Level Trigger SS (output) SCLK, MOSI, MISO Figure 33. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger SS (input) SCLK, MOSI, MISO Figure 34. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor ...

Page 47

... WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control Register. 3.11 LCD Controller This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD controller with various display configurations, refer to the LCD controller chapter of the MC9328MXL Reference Manual. LSCLK ...

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... Non-display region XMAX T8 (1,1) (1,2) T9 T10 Minimum Corresponding Register Value T5+T6 +T7+T9 XMAX MC9328MXL Advance Information, Rev. 5 3.0V ± 0.30V Unit Maximum – Display region Line 1 Line Y T7 (1,X) Unit (VWAIT1·T2)+T5+T6+T7+T9 XMAX+T5+T6+T7+T9+T10 VWIDTH·(T2) VWAIT2·(T2) HWIDTH+1 HWAIT2+1 Freescale Semiconductor ...

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... SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 37, SCLK is always active. • For T9 non-display region, VSYN is non-active used as an reference. • XMAX is defined in pixels. Freescale Semiconductor Minimum Corresponding Register Value MC9328MXL Advance Information, Rev. 5 Specifications Unit HWAIT1 ...

Page 50

... Valid Data 7 Valid Data 6a 1.8V ± 0.10V Minimum Maximum 0 25 400 6/33 – 15/75 – – 10/50 (5.00) – 14/67 (6.67) 5.7/5.7 – 5.7/5.7 – 5.7/5.7 – 5.7/5.7 – MC9328MXL Advance Information, Rev Valid Data Valid Data 6b 3.0 ± 0.30V Minimum Maximum 0 25/5 0 400 10/50 – 10/50 – – 10/50 3 – 10/50 3 5/5 – 5/5 – 5/5 – 5/5 – ...

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... ID Host Command Content CRC E Z ****** cycles CR Host Command Content CRC ****** MC9328MXL Advance Information, Rev. 5 Specifications Host Active Definition Start bit (0) Transmitter bit (Host = 1, Card = 0) One-cycle pull-up (1) End bit (1) CID/OCR Content Identification Timing CID/OCR Content ...

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... Timing response end to next CMD start (data transfer mode) N cycles CC ****** CRC Timing of command sequences (all modes) until the card sees a stop transmission command. AC MC9328MXL Advance Information, Rev. 5 Response Content CRC Host Command Content CRC Host Command Content ...

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... Timing of stop command Valid Read Data (CMD12, data transfer mode) Figure 41. Timing Diagrams at Data Read cycles. The data is suffixed with CRC check bits to allow the card to check MC9328MXL Advance Information, Rev. 5 Specifications Response Content CRC ***** Read Data Timing of single block read ...

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... Specifications 54 Figure 42. Timing Diagrams at Data Write MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor ...

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... The stop transmission command may occur when the card is in different states. Figure 43 shows the different scenarios on the bus. Figure 43. Stop Transmission During Different Scenarios Freescale Semiconductor MC9328MXL Advance Information, Rev. 5 Specifications 55 ...

Page 56

... NAC 2 TAAC + NSAC NRC 8 – NCC 8 – NWR 2 – NST 2 2 MC9328MXL Advance Information, Rev. 5 Unit Parameter MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL) Clock Command response cycle cycles Clock Identification response cycles cycle Clock ...

Page 57

... L H Interrupt Period Figure 44. SDIO IRQ Timing Diagram CMD52 CRC Figure 45. SDIO ReadWait Timing Diagram MC9328MXL Advance Information, Rev. 5 Specifications ****** IRQ Block Data S E ****** ...

Page 58

... MS_SCLKO low pulse width 1 9 MS_SCLKO rise time 1 10 MS_SCLKO fall time Figure 46. MSHC Signal Timing Diagram Parameter 1 1 MC9328MXL Advance Information, Rev 3.0 ± 0.3V Unit Minimum Maximum – 25 MHz 20 – – ...

Page 59

... SDIO pin when the pin direction changes the MSC2[RED] bit = 0, MSHC samples MS_SDIO input data at MS_SCLKO rising edge the MSC2[RED] bit = 1, MSHC samples MS_SDIO input data at MS_SCLKO falling edge. Freescale Semiconductor Parameter 1,2 MC9328MXL Advance Information, Rev. 5 Specifications 3.0 ± 0.3V Unit Minimum Maximum – – ...

Page 60

... The bank and other address lines are driven to the selected address. The second command Figure 47. PWM Output Timing Diagram 1.8V ± 0.10V Minimum Maximum 3.3 – 7.5 – – 5 – 6.67 5.7 – 5.7 – MC9328MXL Advance Information, Rev 3.0V ± 0.30V Unit Minimum Maximum 0 100 MHz 5/10 – ns 5/10 – ns – 5/10 ns – 5/ – – ...

Page 61

... Freescale Semiconductor COL/ Data 3S 3H Note: CKE is high during the read/write cycle. Table 23. SDRAM Timing Parameter Table 1.8V ± 0.10V Minimum 2.67 6 11.4 3.42 MC9328MXL Advance Information, Rev. 5 Specifications 3.0V ± 0.30V Maximum Minimum Maximum – 4 – – 4 – – 10 – – 3 – ...

Page 62

... Data out hold time 7 Data out high-impedance time ( Data out high-impedance time ( Data out high-impedance time ( Active to read/write command period ( SDRAM clock cycle time. This settings can be found in the MC9328MXL reference manual. RCD 62 1.8V ± 0.10V Minimum Maximum 2.28 3.42 2.28 – – ...

Page 63

... Precharge cycle period 7 Active to read/write command delay Freescale Semiconductor ROW/BA 1.8V ± 0.10V Minimum Maximum 2.67 6 11.4 3.42 2. RCD MC9328MXL Advance Information, Rev. 5 Specifications COL/ DATA 3.0V ± 0.30V Minimum Maximum – 4 – – 4 – – 10 – – 3 – – 2 – – ...

Page 64

... Table 24. SDRAM Write Timing Parameter Table (Continued) Ref Parameter No. 8 Data setup time 9 Data hold time 1. Precharge cycle timing is included in the write timing diagram and t = SDRAM clock cycle time. These settings can be found in the MC9328MXL reference RP RCD manual. SDCLK RAS CAS ...

Page 65

... No. 3 SDRAM clock cycle time 4 Address setup time 5 Address hold time 6 Precharge cycle period 7 Auto precharge command period 1. t and t = SDRAM clock cycle time. These settings can be found in the MC9328MXL reference RP RC manual. SDCLK CS RAS CAS WE ADDR BA DQ DQM CKE Figure 51. SDRAM Self-Refresh Cycle Timing Diagram Freescale Semiconductor 1.8V ± ...

Page 66

... USBD_ROE active to ROE_VPO USBD_VPO low USBD_ROE active to ROE_VMO USBD_VMO high USBD_VPO high to VPO_ROE USBD_ROE deactivated PERIOD 2 1.8V ± 0.10V Minimum Maximum 83.14 83.47 81.55 81.98 83.54 83.80 MC9328MXL Advance Information, Rev VMO_ROE 3 t VPO_ROE t FEOPT 5 3.0V ± 0.30V Unit Minimum Maximum 83.14 83.47 ns 81.55 81.98 ns 83.54 83.80 ns Freescale Semiconductor ...

Page 67

... Parameter Receiver SE0 interval of EOP FEOPR Freescale Semiconductor 1.8V ± 0.10V Minimum Maximum 248.90 249.13 160.00 175.00 11.97 12.03 1.8V ± 0.10V Minimum Maximum 82 MC9328MXL Advance Information, Rev. 5 Specifications 3.0V ± 0.30V Unit Minimum Maximum 248.90 249.13 160.00 175.00 11.97 12.03 Mb FEOPR 3.0V ± 0.30V Minimum Maximum – ...

Page 68

... Figure 54. Definition of Bus Timing for I 2 Table 28 Bus Timing Parameter Table 1.8V ± 0.10V Minimum Maximum 182 0 11.4 80 480 182.4 MC9328MXL Advance Information, Rev 3.0V ± 0.30V Minimum Maximum – 160 – 171 0 150 – 10 – – 120 – ...

Page 69

... Note: SRXD input in synchronous mode only. Figure 55. SSI Transmitter Internal Clock Timing Diagram SRCK Output SRFS (bl) Output SRFS (wl) Output SRXD Input Figure 56. SSI Receiver Internal Clock Timing Diagram Freescale Semiconductor MC9328MXL Advance Information, Rev. 5 Specifications ...

Page 70

... STCK high to STFS (bl) high 3 SRCK high to SRFS (bl) high 1.8V ± 0.10V Minimum Maximum 1 (Port C Primary Function 1 95 – 3 1.5 4.5 3 -1.2 -1.7 MC9328MXL Advance Information, Rev 3.0V ± 0.30V Unit Minimum Maximum 2 ) 83.3 – ns 1.3 3.9 ns -1.1 -1.5 ns Freescale Semiconductor ...

Page 71

... MC9328MXL Advance Information, Rev. 5 Specifications 3.0V ± 0.30V Unit Minimum Maximum 2.2 3.8 ns 0.1 -0.8 ns 1.3 3.9 ns -1.1 -1.5 ns 2.2 3.8 ns 0.1 -0.8 ns 12.5 13.8 ns 0.8 2.7 ns 0.5 2.8 ns 11.3 11.9 ns 18.5 – – 81.4 – ns 40.7 – ns 40.7 – ...

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... Minimum Maximum 18.47 1.14 0 15.4 0 1.14 0 1.8V ± 0.10V Minimum Maximum 1 (Port B Alternate Function 1 95 – 3 1.7 4.8 3 -0.1 1.0 3 3.08 5.24 3 1.25 2.28 3 1.71 4.79 3 -0.1 1.0 3 3.08 5.24 MC9328MXL Advance Information, Rev. 5 3.0V ± 0.30V Minimum Maximum 28.5 16.2 25.0 – 1.0 – – 0 – – 13.5 – – 0 – – 1.0 – – 0 – 3.0V ± 0.30V Minimum Maximum 2 ) 83.3 – 1.5 4.2 -0.1 1 ...

Page 73

... MC9328MXL Advance Information, Rev. 5 Specifications 3.0V ± 0.30V Unit Minimum Maximum 1.1 2.0 ns 13.1 14.2 ns 1.1 3.0 ns 2.2 3.5 ns 10.9 12.8 ns 17.5 – – 81.4 – ns 40.7 – ns 40.7 – 81.4 ...

Page 74

... SSI module selects the input based on FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function bit length word length. 74 1.8V ± 0.10V Minimum Maximum 18.81 – 0 – 1.14 – 0 – MC9328MXL Advance Information, Rev. 5 3.0V ± 0.30V Unit Minimum Maximum 2 ) 16.5 – – 1.0 – ...

Page 75

... VSYNC HSYNC PIXCLK DATA[7:0] Figure 59. Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge Freescale Semiconductor 2 Valid Data Valid Data 3 4 MC9328MXL Advance Information, Rev. 5 Specifications × 32 image data receive FIFO, and Valid Data 75 ...

Page 76

... For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns. positive duty cycle = 5ns => max rise time allowed = 4ns 76 2 Valid Data Valid Data 3 4 Parameter Min 180 10.42 10.42 0 MC9328MXL Advance Information, Rev Valid Data Max Unit – ns – ns – ns – ns – ns – ...

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... The parameters for the timing diagrams are listed in Table 32 on page 78. VSYNC PIXCLK DATA[7:0] Figure 61. Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge Freescale Semiconductor 1 Valid Data Valid Data 2 3 MC9328MXL Advance Information, Rev. 5 Specifications Valid Data 77 ...

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... Valid Data Valid Data 2 3 Parameter Min 180 1 1 10.42 10.42 0 MC9328MXL Advance Information, Rev Valid Data Max Unit – ns – ns – ns – ns – ...

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... D10 EB0 CS3 D6 R EB2 EB3 A1 CS4 D8 T NVSS1 A2 OE CS5 CS2 1. burst clock Table 33. MC9328MXL 256 MAPBGA Pin Assignments NVDD4 NVSS3 UART1_ UART1_ NVDD3 RTS RXD USBD_VP SSI0_ SSI0_ SPI1_ N.C. RXCLK TXCLK SCLK UART2_ UART2_ SSI0_ UART1_ N ...

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... NVDD1 M D16 D15 D13 D10 D12 EB0 P D14 D11 EB1 EB2 1. burst clock Table 34. MC9328MXL 225 PBGA Pin Assignments USBD_VM SSI0_ SSI0_ SPI1_RDY RXFS TXCLK USBD_ SSI0_ UART1_ SPI1_SS VMO RXDAT TXD USBD_ UART2_ SSI0_ UART1_ ...

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... INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994. 3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS. Figure 63. MC9328MXL 256 MAPBGA Mechanical Drawing Freescale Semiconductor Case Outline 1367 MC9328MXL Advance Information, Rev. 5 Pin-Out and Package Information ...

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... MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. Figure 64. MC9328MXL 225 PBGA Mechanical Drawing 82 Case Outline 1304B MC9328MXL Advance Information, Rev. 5 SIDE VIEW Freescale Semiconductor ...

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... Freescale Semiconductor NOTES MC9328MXL Advance Information, Rev ...

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... Tai Po Industrial Estate Tai Po, N.T., Hong Kong 852-26668334 Home Page: www.freescale.com MC9328MXL/D Rev. 5 08/2004 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...