UPD17073 NEC, UPD17073 Datasheet - Page 130

• Manufacturer Part Number: UPD17073
• Description: 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM
• Manufacturer: NEC

15.2.3 Programmable divider, PLL data register, and PLL data set register
by the PLL data register is transferred by the PLL data set register to the swallow counter and programmable counter.
130
(1) Configuration and functions of PLL data register
(2) Configuration and function of PLL data set register
(3) Relations between value N of programmable divider and output frequency
A division value is set to the swallow counter and programmable counter by the PLL data register. The value set
The swallow counter and programmable counter are 5-bit and 12-bit binary counters.
The value to be divided is called an “N value”.
For how to set the division value (N value) in each division mode, refer to 15.6 Using PLL Frequency Synthesizer.
The configuration of the PLL data register is shown in Figure 15-4.
The higher 12 bits of the 16-bit PLL data register are valid in the direct division mode, and all the 17 bits of
the register are valid in the pulse swallow mode.
In the direct division mode, the 12 valid register bits are set to the programmable counter.
In the pulse swallow mode, the higher 12 bits are set to the programmable counter, and the remaining lower
5 bits are set to the swallow counter.
Figure 15-5 shows the configuration of the PLL data set register.
By writing “1” to the PLLPUT flag, the division value set by the PLL data register is transferred to the swallow
counter and programmable counter.
After the data has been set, the PLLPUT flag is reset to “0”.
Value “N” set to the PLL data register and the frequency “f
divider are determined as follows.
For details, refer to 15.6 Use of PLL Frequency Synthesizer.
(a) In direct division mode (MF)
(b) In pulse swallow mode (HF, VHF)
f
f
Note
N
N
=
=
f
N
f
IN
N
In VHF mode, frequency f
input to the programmable divider. Therefore, f
IN
N: 12 bits
N: 17 bits
IN
of the signal input from VCOH pin is divided by two immediately before
N
” that is divided and output by the programmable
N
=
1
2
f
N
IN
in the VHF mode.
PD17072,17073