UPD17073 NEC, UPD17073 Datasheet - Page 180

• Manufacturer Part Number: UPD17073
• Description: 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM
• Manufacturer: NEC

19.3.5
is to be executed when the CE pin happens to be at the high level.
“STOP XTAL” in <2> is executed after processing A has been performed.
is treated as a no-operation (“NOP”) instruction.
main processing, and malfunctioning may take place.
malfunctioning does not take place even after the execution enters the main processing.
timer 0 carry FF is set next time.
180
The clock stop instruction (“STOP s”) is valid only when the CE pin is at the low level.
Therefore, it is necessary to design program taking into consideration the chance that the “STOP s” instruction
Here is an example:
In this program example, the status of the CE pin is detected in <1>. If it is at the low level, the clock stop instruction
However, if the CE pin goes high while the “STOP XTAL” instruction is executed as shown below, the instruction
At this time, assuming that the branch instruction “BR $-1” in <3> is missing, the program execution enters the
Therefore, either insert the branch instruction as shown in <3>, or the program must be designed so that
If the CE pin is at high level when the “STOP XTAL” instruction is executed, CE reset is effected when the basic
Example
CEJDG:
MAIN:
Notes on using clock stop instruction
V
CE pin
;
;
;
DD
<1>
<2>
<3>
XTAL
SKF1
BR
STOP
BR
BR
Main processing
Processing A
3 V
0 V
H
L
DAT
CE
MAIN
XTAL
$-1
CEJDG
CE pin is detected
0000B
<1>
processing
Main
<1>
<1>
Processing
A
<2> STOP XTAL
Treated as "NOP"
because CE pin
is high
; Symbol definition of clock stop condition
; Embedded macro
; Detects input level of CE pin
; Branches to main processing
; if CE = high level
; Processing when CE = low
; Clock stops
Program starts from
address 0 in synchronization
with setting of basic timer 0
carry FF (CE reset)
PD17072,17073