UPD17073 NEC, UPD17073 Datasheet - Page 27

• Manufacturer Part Number: UPD17073
• Description: 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM
• Manufacturer: NEC

4.2 Configuration and Function of Data Memory
7H row addresses and 0FH column addresses.
paragraphs 4.2.1 through 4.2.8.
manipulation instructions.
4.2.1 System registers (SYSREG)
exist at addresses 74H through 7FH of each bank.
and PSWORD (program status word: addresses 7EH and 7FH) can be manipulated.
4.2.2 Data buffer (DBF)
hardware.
4.2.3 General registers
and cannot be moved.
instruction.
areas.
4.2.4 LCD segment registers
used to set the display data of the LCD controller/driver.
4.2.5 Port registers
BANK1, and are used to set the output data of each general-purpose port and read the data of the input ports.
4.2.6 Peripheral control registers
conditions of the peripheral hardware (such as PLL, serial interface, A/D converter, IF counter, and timer).
Figure 4-2 shows the configuration of the data memory.
As shown in this figure, the data memory is divided into three banks, and each bank consists of 128 nibbles with
In terms of function, the data memory can be divided into six blocks each of which is described in the following
The contents of the data memory can be operated, compared, judged, and transferred in 4-bit units by data memory
Table 4-1 lists the data memory manipulation instructions.
The system registers are allocated to addresses 74H through 7FH.
These registers are allocated independently of the bank and directly control the CPU. The same system registers
With the PD17073, only AR (address register: addresses 75H through 77H), BANK (bank register: address 79H),
For details, refer to 5. SYSTEM REGISTER (SYSREG).
The data buffer is allocated to addresses 0CH through 0FH of BANK0.
The data buffer reads the constant data in the program memory (table reference), and transfers data with peripheral
For details, refer to 9. DATA BUFFER (DBF).
Operations and data transfer between the general registers and data memory can be executed with a single
The general registers can be controlled by data memory manipulation instructions, like the other data memory
For details, refer to 6. GENERAL REGISTER (GR).
The LCD segment registers are allocated to addresses 41H through 4FH of BANK1 of the data memory, and are
For details, refer to 18. LCD CONTROLLER/DRIVER.
The port registers are allocated to addresses 70H through 73H of BANK0 and addresses 70H through 73H of
For details, refer to 10. GENERAL-PURPOSE PORT.
With the PD17073, the general registers are fixed at row address 0 of BANK0, i.e., addresses 00H through 0FH,
The peripheral control registers are allocated to addresses 50H through 6FH of BANK1 and are used to set the
For details, refer to 8. PERIPHERAL CONTROL REGISTER.
PD17072,17073
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