GAL20V8 Lattice Semiconductor, GAL20V8 Datasheet - Page 15

• Manufacturer Part Number: GAL20V8
• Description: High Performance E2CMOS PLD Generic Array Logic
• Manufacturer: Lattice Semiconductor

Note: fmax with external feedback is calculated from measured
tsu and tco.
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
3-state levels are measured 0.5V from steady-state active
level.
GAL20V8B Output Load Conditions (see figure)
f
Switching Test Conditions
Input Pulse Levels
Input Rise and
Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
max Descriptions
Test Condition
A
B
C
Active High
Active Low
Active High
Active Low
f
max with External Feedback 1/(
f
max with No Feedback
LOGIC
ARRAY
t
L O G I C
A R R A Y
su +
t
s u
t
h
GAL20V8C
GAL20V8B
200
200
200
R
1
REGISTER
R EG I S T E R
CLK
C L K
390
390
390
390
390
2 – 3ns 10% – 90%
1.5ns 10% – 90%
R
2
t
GND to 3.0V
See Figure
t
su+
c o
1.5V
1.5V
t
co)
50pF
50pF
50pF
5pF
5pF
C
L
15
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
GAL20V8C Output Load Conditions (see figure)
Test Condition
A
B
C
FROM OUTPUT (O/Q)
UNDER TEST
Active High
Active Low
Active High
Active Low
f
*C
max with Internal Feedback 1/(
Specifications GAL20V8
L
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
LOGIC
ARRAY
R
2
200
200
200
R
+5V
t
cf
t
1
pd
REGISTER
R
CLK
1
200
200
200
200
200
R
C *
2
t
L
su+
TEST POINT
t
cf)
50pF
50pF
50pF
5pF
5pF
C
L