M36L0T7050 ST Microelectronics, M36L0T7050 Datasheet - Page 4

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M36L0T7050

Manufacturer Part Number
M36L0T7050
Description
128Mbit (Multiple Bank / Multi-Level / Burst) Flash Memory 32Mbit (2M x16) PSRAM
Manufacturer
ST Microelectronics
Datasheet

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M36L0T7050T0, M36L0T7050B0
SUMMARY DESCRIPTION
The M36L0T7050T0 and M36L0T7050B0 com-
bine two memory devices in a Multi-Chip Package:
a 128-Mbit, Multiple Bank Flash memory, the
M30L0T7000T0 or M30L0T7000B0, and a 32-Mbit
PseudoSRAM, the M69AW048B. Recommended
operating conditions do not allow more than one
memory to be active at the same time.
The memory is offered in a Stacked TFBGA88
(8x10mm, 8x10 ball array, 0.8mm pitch) package.
In addition to the standard version, the packages
are also available in Lead-free version, in compli-
ance with JEDEC Std J-STD-020B, the ST ECO-
PACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
All packages are compliant with Lead-free solder-
ing processes.
The memory is supplied with all the bits erased
(set to ‘1’).
Figure 2. Logic Diagram
4/18
A0-A22
WP
RP
UB
W
E1
E2
G
LB
E
G
W
L
K
F
F
F
F
P
P
P
F
F
F
P
P
P
23
V
DDF
M36L0T7050T0
M36L0T7050B0
V
DDQ
V SS
V
PPF
V
DDP
16
DQ0-DQ15
WAIT
AI08734
F
Table 1. Signal Names
Note: 1. A22-A21 are not connected to the PSRAM component.
A0-A22
DQ0-DQ15
V
V
V
V
V
NC
DU
Flash Memory Signals
L
E
G
W
RP
WP
K
WAIT
PSRAM Signals
E1
G
W
E2
UB
LB
F
DDF
DDQ
PPF
SS
DDP
F
F
F
P
F
P
P
P
P
F
P
F
F
(1)
Address Inputs
Common Data Input/Output
Power Supply for Flash Memory
Flash Memory Power Supply for I/O
Buffers
Flash Optional Supply Voltage for Fast
Program and Erase
Ground
PSRAM Power Supply
Not Connected Internally
Do Not Use as Internally Connected
Latch Enable Input
Chip Enable Input
Output Enable Input
Write Enable Input
Reset Input
Write Protect Input
Burst Clock
Wait Data in Burst Mode
Chip Enable Input
Output Enable Input
Write Enable Input
Power-down Input
Upper Byte Enable Input
Lower Byte Enable Input

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