M36L0T7050 ST Microelectronics, M36L0T7050 Datasheet - Page 7

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M36L0T7050

Manufacturer Part Number
M36L0T7050
Description
128Mbit (Multiple Bank / Multi-Level / Burst) Flash Memory 32Mbit (2M x16) PSRAM
Manufacturer
ST Microelectronics
Datasheet

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fast read/write cycles to be achieved with the com-
mon I/O data bus.
Write Enable (W
trols the Bus Write operation of the memory.
Upper Byte Enable (UB
able, UB
Inputs/Outputs (DQ8-DQ15) to or from the upper
part of the selected address during a Write or
Read operation.
Lower Byte Enable (LB
able, LB
Inputs/Outputs (DQ0-DQ7) to or from the lower
part of the selected address during a Write or
Read operation.
V
supply to the internal cores of the Flash memory
component. It is the main power supply for all
Flash operations (Read, Program and Erase).
V
age supplies the power for all operations (Read,
Write, etc.) and for driving the refresh logic, even
when the device is not being accessed.
V
supply for the Flash Memory I/O pins. This allows
all Outputs to be powered independently of the
Flash Memory core power supply, V
V
Flash control input and a Flash power supply pin.
DDF
DDP
DDQ
PPF
Program Supply Voltage. V
Supply Voltage. V
Supply Voltage. The V
Supply Voltage. V
P
P
, gates the data on the Lower Byte Data
, gates the data on the Upper Byte Data
P
). The Write Enable, W
P
DDF
P
DDQ
). The Lower Byte En-
). The Upper Byte En-
provides the power
provides the power
DDP
PPF
DDF
Supply Volt-
.
is both a
P
, con-
The two functions are selected by the voltage
range applied to the pin.
If V
V
age lower than V
tion against Program or Erase, while V
enables these functions (see Tables
Characteristics for the relevant values). V
only sampled at the beginning of a Program or
Erase; a change in its value after the operation has
started does not have any effect and Program or
Erase operations continue.
If V
supply pin. In this condition V
until the Program/Erase algorithm is completed.
V
ence for all voltage measurements in the Flash
(core and I/O Buffers) and PSRAM chips.
Note: Each Flash memory device in a system
should have their supply voltage (V
V
decoupled with a 0.1µF ceramic capacitor
close to the pin (high frequency, inherently low
inductance capacitors should be as close as
possible to the package). See
Measurement Load
widths should be sufficient to carry the re-
quired V
PPF
SS
DDF2
PPF
PPF
Ground. V
is seen as a control input. In this case a volt-
) and the program supply voltage V
is kept in a low voltage range (0V to V
is in the range of V
PPF
M36L0T7050T0, M36L0T7050B0
program and erase currents.
SS
PPLKF
is the common ground refer-
Circuit. The PCB track
gives an absolute protec-
PPHF
PPF
it acts as a power
must be stable
Figure 6., AC
7
PPF
and 8, DC
DDF1
> V
PPF
DDQ
PP1F
and
7/18
PPF
is
)

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