WS57C71C-1 STMicroelectronics, WS57C71C-1 Datasheet
WS57C71C-1
Manufacturer Part Number
WS57C71C-1
Description
MILITARY HIGH SPEED 32K x 8 CMOS PROM/RPROM
Manufacturer
STMicroelectronics
Datasheet
1.WS57C71C-1.pdf
(2 pages)
MODE SELECTION
•
•
•
The WS57C71C is a High Performance 256K UV Erasable Electrically Re-Programmable Read Only Memory
(RPROM). It is manufactured in an advanced CMOS technology and utilizes WSI's patented self-aligned split gate
EPROM cell.
The industry standard PROM pin configuration of the WS57C71C provides an easy upgrade path from a 16K x 8
device.
This RPROM is capable of operating at speeds as fast as 35 ns address access time, which enables it to be used
directly with today's fast microprocessors and DSP processors without introducing any wait states. All inputs and
outputs are TTL compatible. The WS57C71C is a low power device even when operated at its fastest speed. The
DIP version is packaged in a 300 mil wide DIP package saving board space for the user.
PRODUCT SELECTION GUIDE
Ultra-Fast Access Time
— 45 ns
Low Power Consumption
Fast Programming
MODE
Read
Output
Disable
Output
Disable
Output
Disable
Program
Program
Verify
Program
Inhibit
Address Access Time (Max)
CS to Output Valid Time (Max)
MILITARY HIGH SPEED 32K x 8 CMOS PROM/RPROM
PINS
Return to Main Menu
PARAMETER
CS1/
V PP
V PP
V PP
V IH
V IL
V IL
X
X
CS2
V IH
V IH
V IL
X
X
X
X
CS3
V IH
V IH
V IL
V IL
V IL
X
X
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
GENERAL DESCRIPTION
OUTPUTS
HIGH Z
High Z
High Z
High Z
D OUT
D OUT
D IN
WS57C71C-45
KEY FEATURES
45 ns
20 ns
PIN CONFIGURATION
NC
O
A
A
A
A
A
A
A
6
5
4
3
2
1
0
0
5
6
7
8
9
10
11
12
13
•
•
•
14 15 16 17 18 19 20
O
4 3 2
1
Chip Carrier
Immune to Latch-UP
— Up to 200 mA
ESD Protection Exceeds 2000V
Available in 300 and 600 Mil DIP
and CLLCC
O
2
NC O
1
WS57C71C-55
32 31 30
3
O
4
55 ns
20 ns
O
29
28
27
26
25
24
23
22
21
5
TOP VIEW
A
A
A
NC
CS3
CS2
CS1/V PP
O
O
12
13
14
7
6
GND
O
O
O
A
A
A
A
A
A
A
A
A
A
9
8
7
6
5
4
3
2
1
0
0
1
2
WS57C71C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
WS57C71C-70
CERDIP
70 ns
30 ns
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
A 10
A 11
A 12
A 13
A 14
CS3
CS2
CS1/V PP
O
O
O
O
O
CC
7
6
5
4
3
4-13
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WS57C71C-1 Summary of contents
Page 1
... It is manufactured in an advanced CMOS technology and utilizes WSI's patented self-aligned split gate EPROM cell. The industry standard PROM pin configuration of the WS57C71C provides an easy upgrade path from a 16K x 8 device. This RPROM is capable of operating at speeds as fast address access time, which enables used directly with today's fast microprocessors and DSP processors without introducing any wait states ...
Page 2
... WS57C71C-55TMB 55 WS57C71C-70TMB 70 NOTE: 9. The actual part marking will not include the initials "WS." PROGRAMMING/ALGORITHMS/ERASURE/PROGRAMMERS The WS57C71C is programmed using Algorithm D shown on page 5-9. For complete data sheet and electrical specifications see page 2-55. Return to Main Menu PACKAGE PACKAGE TYPE DRAWING 28 Pin CERDIP, 0.3" ...