CDP1805 Intersil Corporation, CDP1805 Datasheet
CDP1805
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CDP1805 Summary of contents
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... Counter/Timer con- trol, improved interrupt handling, single-instruction loop counting, and BCD arithmetic. Upwards software and hardware compatibility is maintained when substituting a CDP1805AC or CDP1806AC for other CDP1800-series microprocessors. Pinout is identical except for the replacement of V the replacement of V TEMPERATURE RANGE ...
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... † ME for CDP1805AC V for CDP1806AC DD Schematic IN CDP1851 PIO CONTROL OUT BUS0 - BUS7 FIGURE 1. TYPICAL CDP1805AC, CDP1806AC SMALL MICROPROCESSOR SYSTEM CDP1805AC, CDP1806AC XTAL 38 DMA IN 37 DMA OUT 36 INTERRUPT 35 MWR 34 TPA SC0 33 TPB MRD 32 MA7 ...
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... CDP1805AC, CDP1806AC FIGURE 2. BLOCK DIAGRAM FOR CDP1805AC AND CDP1806AC 3 ...
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... C to +150 STG 0.79mm) from case for CDP1805ACD, CDP1805ACE CDP1806ACD, CDP1806ACE MIN MAX UNITS 0.625 Mbyte MHz DC 2 MHz CDP1805ACD, CDP1805ACE CDP1806ACD, CDP1806ACE (NOTE 3) MIN TYP MAX UNITS - 50 200 1 0.2 0 -0.1 -0 0.1 4 ...
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... Input Pulse Levels = 0. CDP1805AC CDP1806AC (NOTE 5) TYP MAX UNITS 150 275 ns 325 550 ns 275 450 ns 200 325 ns 150 275 ns 375 625 ns 225 400 ns 250 425 ns 250 425 ns 420 650 ...
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... CDP1805AC, CDP1806AC (NOTE 7) TYP MAX UNITS 2T-275 2T -175 ns T/2 -100 T/2 -75 ns T/2 +75 T/2 +100 ns T +180 T +240 ns T +110 T +150 ns 4.5T -440 4.5T -330 ns ...
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... ME is active after clock 31. The time shown can be longer, if for instance, a DMA out operation is performed on internal RAM data, to allow data enough time to be latched into an external device. The internal RAM is automatically deselected at the end of clock 71 independent of ME. † For CDP1805AC only. FIGURE 3. INTERNAL MEMORY OPERATION TIMING WAVEFORMS EXTERNAL MEMORY READ CYCLE ...
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... All measurements are referenced to 50% point of the wave forms. † Shaded areas indicate “don’t care” or undefined state. Multiple transitions may occur during this period. † For the run (RAM only) mode only. † For the run (RAM/ROM) mode only. †† CDP1805AC, CDP1806AC ...
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... A Schmitt Trigger in the oscillator section allows operation with crystal. The CDP1802 Series LOAD mode is not retained. This mode (WAIT, CLEAR = 0) is not allowed on the CDP1805AC and CDP1806AC. A low power mode is provided, which is initiated via the IDLE instruction. In this mode all external signals, except the oscil- lator, are stopped on the low-to-high transition of TPB ...
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... All outputs swing from V recommended input voltage swing is from V Architecture Figure 2 shows a block diagram of the CDP1805AC and CDP1806AC. The principal feature of this system is a regis- ter array (R) consisting of sixteen 16-bit scratchpad regis- ters. Individual registers in the array (R) are designated (selected 4-bit binary code from one of the 4-bit regis- ters labeled N, P, and X ...
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... R(0) register. At the end of the transfer, R(0) is incremented by one so that the pro- cessor is ready to act upon the next DMA byte transfer request. This feature in the CDP1805AC and CDP1806AC architecture saves a substantial amount of logic when fast exchanges of blocks of data are required, such as with mag- netic discs or during CRT-display-refresh cycles ...
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... External Interrupt short branch instructions, the branch will be taken if an interrupt request is pending, regardless of the state of any of the 3 Interrupt Enable flip-flops. The CDP1805AC, CDP1806AC latched counter interrupt request signal will be reset when the branch is taken, when the CPU is reset, or with a LDC instruction with the Counter stopped ...
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... If the counter underflows while the input is low, interrupt will also be set, but counting will continue. 5. Pulse Duration Measurement 2: Operation is identical to Pulse Duration Measurement 1, except EF2 is used as the gate input. CDP1805AC, CDP1806AC MIE COUNTER UNDERFLOW S COUNTER INTERRUPT ...
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... Pin numbers refer to 40 pin DIP. † FIGURE 8. TYPICAL 5MHz CRYSTAL OSCILLATOR R CLOCK† Pin numbers refer to 40 pin DIP. † FIGURE 9. RC NETWORK FOR OSCILLATOR CDP1805AC, CDP1806AC STM COUNTER INH UNDERFLOW OUT 8-BIT ETQ DOWN COUNTER LDC LOAD READ FIGURE 7 ...
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... The function of the modes are defined as follows: Reset The levels on the CDP1805A and CDP1806A external signal lines will asynchronously be forced by RESET to the follow- ing states SC1, SC0 = 0,1 MRD = 1 (EXECUTE) TPB = 0 N0, N1 TPA = 0 MWR = 1 Internal Changes Caused By RESET are Instruction Register is cleared to 00 ...
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... State Transitions The CDP1805A and CDP1806A state transitions are shown in Figure 13. Each machine cycle requires the same period of time, 8 clock pulses, except the initialization cycle (INlT) ENTER RESUME PAUSE RUN PAUSE CLOCK PAUSE t PLH TPA WAIT FIGURE 12A. TPA PAUSE TIMING FIGURE 12 ...
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... Instruction Set The CDP1805AC and CDP1806AC instruction summary is given in Table 1. Hexadecimal notation is used to refer to the 4-bit binary codes. In all registers, bits are numbered from the least significant bit (LSB) to the most significant bit (MSB) starting with 0. R(W): Register designated by W, where TABLE 1 ...
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... SUBTRACT D WITH BORROW, IMMEDIATE SUBTRACT MEMORY DECIMAL SUBTRACT MEMORY SUBTRACT MEMORY IMMEDIATE DECIMAL SUBTRACT MEMORY, IMMEDIATE SUBTRACT MEMORY WITH BORROW DECIMAL SUBTRACT MEMORY WITH BORROW SUBTRACT MEMORY WITH BORROW, IMMEDIATE CDP1805AC, CDP1806AC MNEMONIC OP CODE 2 ANI FA M(R(P)) AND D 2 SHR F6 Shift D Right, LSB(D) 2 SHRC ...
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... SHORT BRANCH IF EF3 = 0 (EF3 = SHORT BRANCH IF EF4 = 1 (EF4 = SHORT BRANCH IF EF4 = 0 (EF4 = SHORT BRANCH ON COUNTER INTERRUPT SHORT BRANCH ON EXTERNAL INTERRUPT CDP1805AC, CDP1806AC MNEMONIC OP CODE 4 DSBI 687F D - M(R(P)) - (NOT DF) R( DECIMAL ADJUST M(R(P)) 2 NBR 38 R( (Note 11 ...
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... LONG SKIP (See NLBR) LONG SKIP LONG SKIP IF D NOT 0 LONG SKIP LONG SKIP LONG SKIP LONG SKIP LONG SKIP IF MIE = 1 CONTROL INSTRUCTIONS IDLE NO OPERATION SET P SET X CDP1805AC, CDP1806AC MNEMONIC OP CODE 3 LBR C0 M(R(P)) 3 NLBR C8 R( (Note 11) 3 ...
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... START ENABLE TOGGLE Q INTERRUPT CONTROL EXTERNAL INTERRUPT ENABLE EXTERNAL INTERRUPT DISABLE COUNTER INTERRUPT ENABLE COUNTER INTERRUPT DISABLE RETURN DISABLE SAVE SAVE INPUT-OUTPUT BYTE TRANSFER OUTPUT 1 OUTPUT 2 OUTPUT 3 OUTPUT 4 OUTPUT 5 CDP1805AC, CDP1806AC MNEMONIC OP CODE 2 SEQ REQ MARK 79 (X, P) THEN P 3 ...
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... This operation effects a branch to any memory location. If the tested condition is not met, the branching address bytes are skipped over, and the next instruction in sequence is fetched and exe- cuted. This operation is taken for the case of unconditional no branch (NLBR). CDP1805AC, CDP1806AC MNEMONIC OP CODE ...
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... After a BCD SUBTRACT instruction denotes no borrow true positive decimal number. Example 99 D -88 M(R(X denotes a borrow ten's complement form. Example 88 D -99 M(R(X the ten's complement of 11, which is the correct answer (with a minus value denoted 0). CDP1805AC, CDP1806AC . ...
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... OUT INP INP INP INP INP 5 CDP1805AC, CDP1806AC DATA OPERATION BUS COUNTER, 00 PRESCALER, CIL; 1 CIE, XIE THEN MIE, 0000 R0 (Note 20) MRP MRP STOP AT TPB ...
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... BRANCH #2 C 0-3, LONG 8-B BRANCH S1#1 C 0-3, LONG 8-B BRANCH #2 C 0-3, LONG 8-B BRANCH S1 LONG SKIP # LONG SKIP CDP1805AC, CDP1806AC DATA OPERATION BUS BUS MRX, D DATA FROM I/O DEVICE BUS MRX, D DATA FROM I/O DEVICE MRX MRX 1 MIE MRX MRX 0 MIE MRX D ...
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... INTERRUPT RUPT RUPT THE FOLLOWING ARE ALL LINKED INSTRUCTIONS “68” PRECEEDS ALL OP CODES, SO THERE IS A DUPLICATE FETCH STPC DTC CDP1805AC, CDP1806AC DATA OPERATION BUS TAKEN M( NOT TAKEN: NO OPERATION MRP NOT TAKEN: NO OPERATION MRP NOT TAKEN: NO OPERATION ...
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... DSMB # DSMB S1 DACI # DACI S1 DSBI CDP1805AC, CDP1806AC DATA OPERATION BUS CNTR - 1 ON EF2 AND TPA HIGH Z CNTR - 1 ON EF2 HIGH Z CNTR - 1 ON EF1 AND TPA HIGH Z CNTR - 1 ON EF1 HIGH Z CNTR STOPPED: D CH, D CNTR ...
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... C DADI # DADI S1 DSMI # DSMI NOTE: 20. Data bus floats for first 2-1/2 clocks of the nine clock initialization cycle; all zeros for remainder of cycle. CDP1805AC, CDP1806AC DATA OPERATION BUS DECIMAL ADJUST DF, D HIGH Z RN.0, RN HIGH Z T MRX RN.0 B MRX ...
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... DADC DADD †‘68’ is used as a linking OPCODE for the double fetch instructions. CDP1805AC, CDP1806AC INSTRUCTION SUMMARY LDN INC DEC SKP BNQ LDA STR † SDB SHRC SMB SAV MARK GLO ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com CDP1805AC, CDP1806AC Input Signals To prevent damage to the input protection circuit, input sig- ...