MACH215-12 Lattice, MACH215-12 Datasheet

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... FINAL MACH215-12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 44 Pins 32 Output Macrocells 32 Input Macrocells Product terms for: — Individual flip-flop clock — Individual asynchronous reset, preset — Individual output enable Commercial PD 14 Industrial PD 67 MHz f CNT GENERAL DESCRIPTION The MACH215 is a member of the high-performance EE CMOS MACH device family ...

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... CLK 44x64 AND Logic Array and Logic Allocator 22 Switch Matrix 22 44x64 AND Logic Array 8 8 and 8 Logic Allocator OE CLK Output Input Macrocells Macrocells 8 8 I/O Cells I/O –I MACH215-12/15/20 I – – CLK /I CLK / 16751E-1 ...

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... CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V = Supply Voltage CC PLCC MACH215-12/15/ I CLK GND 16751E-2 3 ...

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... The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availabil- ity of specific valid combinations and to check on newly released combinations. MACH215-12/15/20 (Com’l) OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS C = Commercial ( +70 C) ...

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... The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availabil- ity of specific valid combinations and to check on newly released combinations. MACH215-14/18/24 (Ind) OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS I = Industrial (– +85 C) ...

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... These choices can be made automatically by the software when it fits the design into the device. Table 2. Register/Latch Operation Configuration D-Register T-Register Latch *Polarity of CLK/LE can be programmed. MACH215-12/15/20 Available Clusters ...

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... I/O pin can be configured as an output, an input bidirectional pin. The feedback from the I/O pin is always available to the switch matrix, regardless of the state of the output buffer or the output macrocell. Q+ See Table MACH215-12/15/20 7 ...

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... Switch Matrix Figure 1. MACH215 PAL Block MACH215-12/15/20 I/O Cell Output M Macro 0 Cell 2 Input Macro Cell 2 I/O Cell Output M Macro 1 Cell 2 Input Macro Cell 2 I/O Cell Output M C Macro 2 0 Cell ...

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... Product Term Cluster Figure 2. Product Term Clusters and the Logic Allocator Individual Asynchronous Preset Sum of Products from Logic Allocator CLK 0 Individual Clock Individual Asynchronous Reset To Switch Matrix Figure 3. Output Macrocell MACH215-12/15/20 To From n–1 n– Macrocell n From To n+1 n+1 Logic Allocator 16751E D/T/L Q ...

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... From Logic Q To I/O Allocator Cell Individual Individual Preset Individual Preset From Logic Q To I/O Allocator Cell Individual Individual Preset Figure 4. Output Macrocell Configurations MACH215-12/15/ Switch Matrix b. Combinatorial, Active Low CLK 0 AR Clock To Switch Matrix d. D-type Register, Active Low ...

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... Figure 6. Input Macrocell Configurations Output Enable Product Term From Output AP D/L Q Figure 5. Input Macrocell From I/O Cell CLK 0 CLK 1 To Switch Matrix Individual Macrocell To Switch Matrix Macrocell Figure 7. I/O Cell MACH215-12/15/20 From I/O Pin 16751E-7 From I/O Cell Input Latch 16751E-8 To Input 16751E-9 11 ...

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... (Note 0 Max (Note 4) OUT MHz CC A (Note 5) and I (or I and OZL IH OZH MACH215-12/15/20 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 95 Unit ...

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... D-type 7 T-type LOW 6 HIGH 6 D-type 66.7 1/( COS T-type 62.5 D-type 83.3 ) CNTS T-type 76.9 83.3 1/( WLS WHS MACH215-12/15/20 (Com’l) Typ Unit = -15 -20 Min Max Min Max Unit ...

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... Parameters measured with 16 outputs switching. 14 -12 Min Max 2 2 D-type 12 T-type 13 LOW 6 HIGH 6 1/( 83.3 WICL WICH MACH215-12/15/20 (Com’l) -15 -20 Min Max Min Max Unit 2 ...

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... VIN = 5.25 V, VCC = Max (Note 3) VIN = 0 V, VCC = Max (Note 3) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 3) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 4) VCC = MHz (Note 5) MACH215-14/18/24 (Ind – +5.5 V Min Typ Max Unit 2 ...

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... D-type 47 T-type 44 50 1/(tWLA + tWHA ) D-type 8.5 T-type LOW 7.5 HIGH 7.5 D-type 53 1/(tSS + tCOS ) T-type 50 D-type 66.5 T-type 61.5 1/(tWLS + tWHS ) 66 19 7.5 MACH215-14/18/24 (Ind) Typ Unit -18 -24 Min Max Min Max Unit ...

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... SA is the t S parameter for asynchronous clocks. 3. Parameters measured with 16 outputs switching. -14 Min Max 17 2 D-type 14.5 T-type 16 LOW 7.5 HIGH 7.5 1/(tWICL + tWICH ) 66.5 2.5 3 20.5 23 8.5 8 7.5 19.5 19.5 14.5 10 19.5 14.5 10 14.5 14.5 MACH215-14/18/24 (Ind) -18 -24 Min Max Min Max Unit 20.5 26.5 ns 2.4 2 19.5 25 66.5 50 MHz 2.5 2 ...

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... Output, LOW I (mA –3 –2 –1 –25 –50 –75 –100 –125 –150 Output, HIGH I (mA –2 – –20 –40 –60 –80 –100 Input MACH215-12/15/ 1.0 16751E- (V) OH 16751E- 16751E-12 ...

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... The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register Frequency (MHz) MACH215-12/15/20 MACH215 16751E-13 19 ...

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... Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. 20 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air MACH215-12/15/20 Typ PLCC Units 15 C/W 40 ...

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... Gate t WL 16751E- Registered Input t HIR Input V T Register Clock t ICO V T Output Register Clock 16751E-19 MACH215-12/15/ 16751E- PDL Latched Output (MACH 2, 3, and GWS Gate Width (MACH 2, 3, and ...

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... Input pulse amplitude 3 Input rise and fall times 2 ns–4 ns typical SIL HIL Latched Input (MACH 2 and 4) t IGOL Latched Input and Output (MACH 2, 3, and 4) MACH215-12/15/ IGO V T 16751E-21 t PDLL SLL V ...

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... Input, I/ Feedback Registered V T Output t ARR Clock V T 16751E- 0.5V OH Outputs + V 0.5V OL Output Disable/Enable MACH215-12/15/ WIGL 16751E-24 Input Latch Gate Width (MACH 2 and 4) t APW 16751E-26 Asynchronous Preset 16751E-27 APR ...

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... Apply Output Commercial 300 390 5 pF MACH215-12/15/20 OUTPUTS Will be Steady Will be Changing from Will be Changing from Changing, State Unknown Center Line is High- Impedance “Off” State KS000010-PAL Test Point 16751E-28 Measured ...

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... All frequencies except f MAX other measured AC parameters. f ured directly. (SECOND CHIP SIR + MACH215-12/15/ However type is the mini- MAX + t ). Usually, this minimum feedback.” MAX . Because this involves no MAXIR MAX + the sum of SIR HIR + t ) ...

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... Min Pattern Data Retention Time Max Reprogramming Cycles 26 bipolar parts result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Min Units 10 Years 20 Years 100 Cycles MACH215-12/15/20 Test Conditions Max Storage Temperature Max Operating Temperature Normal Programming Conditions ...

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... INPUT/OUTPUT EQUIVALENT SCHEMATICS ESD Protection Input 100 k Preload Feedback Circuitry Input I/O MACH215-12/15/20 CC 100 16751E-30 27 ...

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... Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met Power-Up Reset Waveform MACH215-12/15/20 can rise to its steady state, two CC rise must be monotonic. Max 10 See Switching Characteristics V CC ...

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... All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support. On Preload Off Mode Figure 8. Preload/Reset Conflict Set Reset Figure 9. Combinatorial Latch MACH215-12/15/20 Preloaded HIGH Preloaded HIGH 16751E-32 16751E-33 29 ...

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... REF .032 TOP VIEW *For reference only. BSC is an ANSI standard for Basic Space Centering. 34 .062 .083 .042 .056 .009 .015 .090 .120 .165 .180 SIDE VIEW MACH215-12/15/20 .500 .590 REF .630 .013 .021 SEATING PLANE 16-038-SQ PL 044 DA78 6-28-94 ae ...