VRS51C1100-40-L ETC1 [List of Unclassifed Manufacturers], VRS51C1100-40-L Datasheet - Page 45
VRS51C1100-40-L
Manufacturer Part Number
VRS51C1100-40-L
Description
Versa 8051 MCU with 128KB of IAP/ISP Flash
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.VRS51C1100-40-L.pdf
(50 pages)
- Current page: 45 of 50
- Download datasheet (3Mb)
Timing Requirement of the External Clock (VSS = 0v is assumed)
External Program Memory Read Cycle
The following timing diagram provides External Program Memory Read Cycle timing information.
______________________________________________________________________________________________
www.ramtron.com
F
F
IGURE
IGURE
0.45V
VRS51C1100
Vdd - 0.5V
28: T
29: E
IMING
XTERNAL
R
PORT 0
PORT2
EQUIREMENT OF
#PSEN
P
ROGRAM
ALE
20% Vdd-0.1V
M
EMORY
70% Vdd
E
XTERNAL
R
EAD
C
C
LOCK
YCLE
(VSS= 0.0V
TLHLL
TAVLL
A0-A7
IS ASSUMED
TCHCL
TLLAX
P2.0-P2.7 or AB-A15 from DPH
)
TLLPL
TPLAZ
TAVIV
TCLCX
TPLIV
TPLPH
Instruction IN
TCLCH
TCLCL
TPXIX
TPXIZ
TCHCX
A0-A7
A8-A15
page 45 of 50
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