EVAL-ADV7320EB AD [Analog Devices], EVAL-ADV7320EB Datasheet - Page 61

• Manufacturer Part Number: EVAL-ADV7320EB
• Description: Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
• Manufacturer: AD [Analog Devices]

HSYNC / VSYNC OUTPUT CONTROL
The ADV7320/21 has the ability to accept either embedded time codes in the input data, or external Hsync and Vsync signals on
P_HSYNC / P_VSYNC , outputting the respective signals on the P_HSYNC and P_VSYNC pins.
Table 36. Hsync Output Control
HD/ED
Slave Mode
(0x10, bit 2)
x
x
External HSYNC
& VSYNC /Field
Mode
EAV/SAV Mode
x
______________________________
1
2
Table 37. VSYNC Output Control
HD/ED
Slave Mode
(0x10, Bit 2)
x
x
External HSYNC
& VSYNC /Field
Mode
EAV/SAV Mode
EAV/SAV Mode
x
x
1
2
In all HD/ED standards where there is an HSYNC o/p, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video.
ED = enhanced definition.
In all HD/ED standards where there is an HSYNC o/p, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video.
ED = enhanced definition.
2
2
1
1
HD/ED
Sync out Enable
(0x02, Bit 7)
0
0
1
1
1
HD/ED
Sync Out Enable
(0x02, Bit 7)
0
0
1
1
1
1
1
SD
Sync Out Enable
(0x02, Bit 6)
0
1
x
x
x
x
x
SD
Sync Out Enable
(0x02, Bit 6)
0
1
x
x
x
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I2C_VSYNC _gen_sel
(0x14, Bit 2)
x
x
0
0
0
1
1
I2C_HSYNC _gen_sel
(0x14, Bit 1)
x
x
0
0
1
Video
Standard
x
Interlaced
x
All HD interlace
standards
All HD/ED
progressive
standards
All HD/ED stan-
dards except
525p
525p
Signal on S_HSYNC Pin
Tristate
Pipelined SD HSYNC
Pipelined Ext HD/ED HSYNC
Pipelined HD/ED HSYNC
based on AV code H bit
Pipelined HD/ED HSYNC
based on horizontal counter
Signal on
S_VSYNC Pin
Tristate
Pipelined SD
VSYNC / field
Pipelined EXT
HD/ED VSYNC or
field signal
External pipelined
field signal based
on AV code F bit
Pipelined VSYNC
based on AV code
V bit
External pipelined
HD/ED VSYNC
based on vertical
counter
External pipelined
HD/ED VSYNC
based on vertical
counter
ADV7320/ADV7321
Duration
–
See Appendix
5—SD Timing
Modes
As per HSYNC
timing
Same as line
blanking interval
Same as
embedded
HSYNC
Duration
-
See Appendix
5—SD Timing
Modes
As per Ext VSYNC
or field signal
Field
Vertical blanking
interval
Aligned with
serration lines
Vertical blanking
interval