EVAL-CONTROLBRD3 AD [Analog Devices], EVAL-CONTROLBRD3 Datasheet - Page 14

• Manufacturer Part Number: EVAL-CONTROLBRD3
• Description: 16-Bit, 100 kSPS PulSAR ADC in MSOP/QFN
• Manufacturer: AD [Analog Devices]

AD7683
Table 9. Recommended Driver Amplifiers
Amplifier
AD8021
AD8022
OP184
AD8605,
AD8519
AD8031
VOLTAGE REFERENCE INPUT
The AD7683 voltage reference input, REF, has a dynamic input
impedance. It should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source (e.g., an
unbuffered reference voltage like the low temperature drift
ADR43x
the AD8605), a 10 µF (X5R, 0805 size) ceramic chip capacitor is
appropriate for optimum performance.
If desired, smaller reference decoupling capacitor values down
to 2.2 µF can be used with a minimal impact on performance,
especially DNL.
POWER SUPPLY
The AD7683 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 24. This makes the part
ideal for low sampling rates (even of a few Hz) and low battery-
powered applications.
DIGITAL INTERFACE
The AD7683 is compatible with SPI, QSPI, digital hosts, and
DSPs (e.g., Blackfin® ADSP-BF53x or ADSP-219x). The con-
nection diagram is shown in Figure 25 and the corresponding
timing is given in Figure 2.
1000
0.01
100
0.1
10
AD8615
1
reference or a reference buffer using the
10
Figure 24. Operating Current vs. Sampling Rate
Typical Application
Very low noise and high frequency
Low noise and high frequency
Low power, low noise, and low frequency
5 V single-supply, low power
Small, low power, and low frequency
High frequency and low power
100
SAMPLING RATE (SPS)
1k
VDD = 5V
VDD = 2.7V
10k
AD8031
100k
or
Rev. 0 | Page 14 of 16
A falling edge on CS initiates a conversion and the data transfer.
After the fifth DCLOCK falling edge, D
forced low. The data bits are then clocked, MSB first, by subse-
quent DCLOCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the SCK falling edge allows a faster
reading rate, provided it has an acceptable hold time.
LAYOUT
The printed circuit board housing the AD7683 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7683 with all its analog signals on the left side and all its
digital signals on the right side eases this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7683 is used as a shield. Fast switching signals, such as CS or
clocks, should never run near analog signal paths. Crossover of
digital and analog signals should be avoided.
At least one ground plane should be used. It could be common
or split between the digital and analog section. In such a case, it
should be joined underneath the AD7683.
The AD7683 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. That is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and by connecting these pins with wide, low
impedance traces.
Finally, the power supply, VDD, of the AD7683 should be
decoupled with a ceramic capacitor, typically 100 nF, and placed
close to the AD7683. It should be connected using short and
large traces to provide low impedance paths and reduce the
effect of glitches on the power supply lines.
EVALUATING THE AD7683’S PERFORMANCE
Other recommended layouts for the AD7683 are outlined in the
evaluation board for the AD7683 (EVAL-AD7683). The evalu-
ation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the
AD7683
DCLOCK
CS
Figure 25. Connection Diagram
D
OUT
EVAL-CONTROL
CLK
CONVERT
DATA IN
DIGITAL HOST
OUT
is enabled and
BRD2.