EVAL-CONTROLBRD3 AD [Analog Devices], EVAL-CONTROLBRD3 Datasheet - Page 5

• Manufacturer Part Number: EVAL-CONTROLBRD3
• Description: 16-Bit, 100 kSPS PulSAR ADC in MSOP/QFN
• Manufacturer: AD [Analog Devices]

TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; T
Table 5.
Parameter
Throughput Rate
CS Falling to DCLOCK Low
CS Falling to DCLOCK Rising
DCLOCK Falling to Data Remains Valid
CS Rising Edge to D
DCLOCK Falling to Data Valid
Acquisition Time
D
D
OUT
OUT
Fall Time
Rise Time
DCLOCK
D
OUT
OUT
CS
NOTE:
A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES.
D
High Impedance
OUT
A
= −40°C to +85°C, unless otherwise noted.
GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING.
1
t
CSD
t
SUCS
Hi-Z
4
5
0
t
(MSB)
EN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
t
CYC
Figure 2. Serial Interface Timing
Rev. 0 | Page 5 of 16
t
HDO
COMPLETE CYCLE
Symbol
t
t
t
t
t
t
t
t
t
CYC
CSD
SUCS
HDO
DIS
EN
ACQ
F
R
POWER DOWN
Min
20
5
400
(LSB)
Typ
16
14
16
11
11
0
t
DIS
Hi-Z
t
ACQ
Max
100
0
100
50
25
25
AD7683
Unit
kHz
µs
ns
ns
ns
ns
ns
ns
ns