EVAL-SSM2518Z AD [Analog Devices], EVAL-SSM2518Z Datasheet - Page 25

• Manufacturer Part Number: EVAL-SSM2518Z
• Description: Digital Input Stereo, 2 W, Class-D
• Manufacturer: AD [Analog Devices]

Data Sheet
REGISTER SUMMARY (REG_MAP)
Table 12. REG_MAP Register Summary
Reg Name
0x00 Reset_Power_Control
0x01 Edge_Clock_Control
0x02 Serial_Interface_Sample_Rate_Control
0x03 Serial_Interface_Control
0x04 Channel_Mapping_Control
0x05 Left_Volume_Control
0x06 Right_Volume_Control
0x07 Volume_Mute_Control
0x08 Fault_Control_1
0x09 Power_Fault_Control
0x0A DRC_Control_1
0x0B DRC_Control_2
0x0C DRC_Control_3
0x0D DRC_Control_4
0x0E DRC_Control_5
0x0F DRC_Control_6
0x10 DRC_Control_7
0x11 DRC_Control_8
0x12 DRC_Control_9
Bits Bit 7
[7:0] S_RST
[7:0] RESERVED
[7:0] RESERVED SDATA_FMT
[7:0] BCLK_GEN LRCLK_MODE LRCLK_POL SAI_MSB
[7:0] CH_SEL_R
[7:0] L_VOL
[7:0] R_VOL
[7:0] AMUTE
[7:0] OC_L
[7:0] AR_TIME
[7:0] RESERVED PRE_VOL
[7:0] PEAK_ATT
[7:0] DRC_LT
[7:0] DRC_ET
[7:0] DRC_SMAX
[7:0] DRC_ATT
[7:0] HDT_NOR
[7:0] RESERVED
[7:0] RESERVED
Bit 6
RESERVED
RESERVED
OC_R
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Bit 5
NO_BCLK
ANA_GAIN DEEMP_EN VOL_LINK R_MUTE L_MUTE
OT
RESERVED
LIM_EN
DRC_POST_G
Bit 4
MCS
SAI
MRCV
AMP_LPM
COMP_EN EXP_EN
Bit 3
SLOT_WIDTH
CH_SEL_L
DAC_LPM R_PWDN L_PWDN
PEAK_REL
DRC_CT
DRC_NT
DRC_SMIN
DRC_DEC
HDT_NG
RMS_TAV
MAX_AR
Bit 2
EDGE
NG_EN
FS
Bit 1
BCLK_EDGE RESERVED
ARCV
DRC_EN
RESERVED
Bit 0
SPWDN
ASR
M_MUTE
APWDN_EN 0x99 RW
SSM2518
0x05 RW
0x02 RW
0x00 RW
0x57 RW
0x89 RW
0x07 RW
Reset RW
0x00 RW
0x10 RW
0x40 RW
0x40 RW
0x81 RW
0x0C RW
0x7C RW
0x5B RW
0x8C RW
0x77 RW
0x26 RW
0x1C RW